Fault injection into VHDL models: the MEFISTO tool
Authors:
- E. JennEJE. Jenn
- J. ArlatJAJ. Arlat
- M. RimenMRM. Rimen
- J. OhlssonJOJ. Ohlsson
- J. KarlssonJKJ. Karlsson
Top Cited Papers
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 66-75
Abstract
This paper focuses on the integration of the fault injection methodology within the design process of fault-toleran t systems. Due to its wide spectrum of application and hierarchical features, VHDL has been selected as the simulation language to support such an integration. Suitable techniques for injecting faults into VHDL models are identified and depicted. Then, the main features of the MEFISTO environment aimed at supporting these techniques are described. Finally, some preliminary results obtained with MEFISTO are presented and analyzed. Index Terms: Experimental Validation, Fault Injection, Simulation, VHDL, Fault/Error Models.Keywords
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