An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications
Authors:
- 24 February 2015
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 63 (4) , 1211-1218
Abstract
An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS for optical communications is presented. The DAC can convert 1-k symbols stored in the 1-kbyte design-for-test on-chip memory cyclically. By interleaving four 25-GS/s return-to-zero DACs, the highest signal frequency of the 100-GS/s DAC is about 25 GHz and the output image is located beyond 75 GHz. The 3-dB bandwidth exceeds 13 GHz at 100 GS/s. The effective number of bits and spurious-free dynamic range ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from dc up to 24.9 GHz at 100 GS/s, respectively. Transmission rates of 120 and 45 Gb/s are obtained in an electrical and an optical back-to-back experiment, respectively. The DAC test chip consumes 2.5 W from a power supply with multiple outputs of 1.1, 1.5, and 2 V.Keywords
This publication has 6 references indexed in Scilit:
- An 8-bit 100-GS/s distributed DAC in 28-nm CMOS2014
- Advances in High-Speed DACs, ADCs, and DSP for Optical Coherent TransceiversJournal of Lightwave Technology, 2014
- Generation of a Digitally Shaped 55-GBd 64-QAM Single-Carrier Signal Using Novel High-Speed DACs2014
- A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane CommunicationsIEEE Journal of Solid-State Circuits, 2008
- A Simple Parameter Extraction Method of Spiral On-Chip InductorsIEEE Transactions on Electron Devices, 2005
- Parallel-path digital-to-analog converters for Nyquist signal generationIEEE Journal of Solid-State Circuits, 2004