SEU emulation in industrial SoCs combining microprocessor and FPGA
- 1 February 2018
- journal article
- research article
- Published by Elsevier in Reliability Engineering & System Safety
- Vol. 170, 53-63
Abstract
No abstract availableKeywords
Funding Information
- Ministerio de Economía y Competitividad (TEC2014-53785-R)
- Research and Education Unit (UFI11/16)
This publication has 33 references indexed in Scilit:
- SEU Rate in Avionics: From Sea Level to High AltitudesIEEE Transactions on Nuclear Science, 2015
- FPGA based fault-tolerant control on an interleaved DC/DC boost converter for fuel cell electric vehicle applicationsInternational Journal of Hydrogen Energy, 2015
- Experimental Characterization and Simulation of Electron-Induced SEU in 45-nm CMOS TechnologyIEEE Transactions on Nuclear Science, 2014
- A fault tolerant architecture to avoid the effects of Single Event Upset (SEU) in avionics applicationsMeasurement, 2014
- Design of 65 nm CMOS SRAM for Space Applications: A Comparative StudyIEEE Transactions on Nuclear Science, 2014
- Enabling the usage of UML in the verification of railway systems: The DAM-rail approachReliability Engineering & System Safety, 2013
- Fault tolerant system design and SEU injection based testingMicroprocessors and Microsystems, 2013
- Basic concepts and taxonomy of dependable and secure computingIEEE Transactions on Dependable and Secure Computing, 2004
- Analyzing Reliability—A Simple Yet Rigorous ApproachIEEE Transactions on Industry Applications, 2004
- A tutorial on built-in self-test. I. PrinciplesIEEE Design & Test of Computers, 1993