22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces

The trend of multi-chip modules (MCMs), die-to-die (D2D), and chiplet interfaces (e.g. UCIe) requires high-bandwidth densities while minimizing power consumption [1], [3], [4], [11]–[13]. Single-ended (SE) PAM3 signaling has been adopted in GDDR7 [2] as a high-bandwidth solution, increasing the data rate by 150%, compared to NRZ (PAM2) using the same baud rate. SE PAM3 signaling can also be applied to chiplet interfaces, but it faces challenges (Fig. 22.1.1): (1) the RX requires large-area reference-voltage $(\mathrm{V}_{\text{refp}}$ & $\mathrm{V}_{\text{refn}})$ generators. (2) Matching RX and TX references is challenging, and discrepancies result in a TX-RX reference offset. (3) TX drivers generate simultaneous switching noise (SSN) of up to a few hundred millivolts on $\mathrm{V}_{\text{DI}}$ in TX die [3]; this noise coupled to TX data and cannot be rejected by the RX, thereby degrading voltage margins. (4) Reducing channel pitch increases crosstalk, and PAM3 is $2\times$ more vulnerable to crosstalk than NRZ.