Different Dielectrics for Source, Drain and Channel Regions of 1D Nanowire MOSFETs and TFETs

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Abstract
This work compares the changes in performance of a carbon nanotube CNT-based n-i-n metal-oxide-semiconductor MOSFET and p-i-n tunnel field effect transistor TFET based on different dielectric values of gate κc and source/drain regions κsd. The results prove that at a constant κsd a higher κc improves transconductance gm, output conductance gd, ON-state current, subthreshold swing SS and may lower the threshold voltage VT. However, at a constant κc for an n-i-n MOSFET the performance does not change significantly with κsd, but gd increases. For the p-i-n TFET gm, gd and ON-state current degrade prominently while the minimum current declines and SS may improve. Also two different dielectrics for source κs and drain κd could provide TFET with a lower power-higher performance characteristic. The results are given based on certified NEGF formalism and are explained based on semiclassical discussion with respect to energy band diagram concept. This method simplifies the realization of device's performance optimization. Due to 1D transport properties of CNTs the results could be applied to any device with 1D electronic transport characteristics.

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