Temporal Logic Formalisation of ISO 34502 Critical Scenarios: Modular Construction with the RSS Safety Distance
Authors:
- Jesse ReimannJRJesse Reimann
- Nico MansionNMNico Mansion
- James HaydonJHJames Haydon
- Benjamin BrayBBBenjamin Bray
- Agnishom ChattopadhyayACAgnishom Chattopadhyay
- Sota SatoSSSota Sato
- Masaki WagaMWMasaki Waga
- Étienne AndréÉAÉtienne André
- Ichiro HasuoIHIchiro Hasuo
- Naoki UedaNUNaoki Ueda
- Yosuke YokoyamaYYYosuke Yokoyama
Preprint
Abstract
As the development of autonomous vehicles progresses, efficient safety assurance methods become increasingly necessary. Safety assurance methods such as monitoring and scenario-based testing call for formalisation of driving scenarios. In this paper, we develop a temporal-logic formalisation of an important class of critical scenarios in the ISO standard 34502. We use signal temporal logic (STL) as a logical formalism. Our formalisation has two main features: 1) modular composition of logical formulas for systematic and comprehensive formalisation (following the compositional methodology of ISO 34502); 2) use of the RSS distance for defining danger. We find our formalisation comes with few parameters to tune thanks to the RSS distance. We experimentally evaluated our formalisation; using its results, we discuss the validity of our formalisation and its stability with respect to the choice of some parameter values.Keywords
All Related Versions
- Version 1, 2024-03-27, ArXiv
- Published version: , 186.
This publication has 23 references indexed in Scilit:
- Cut-Out Scenario Generation With Reasonability Foreseeable Parameter Range From Real Highway Dataset for Autonomous Vehicle AssessmentIEEE Access, 2023
- Critical scenario identification for realistic testing of autonomous driving systemsSoftware Quality Journal, 2022
- Logical Scenarios Parameterization for Automated Vehicle Safety Assessment: Comparison of Deceleration and Cut-In Scenarios From Japanese and German HighwaysIEEE Access, 2022
- Multi-armed Bandits for Boolean Connectives in Hybrid System Falsification2019
- STLInspector: STL Validation with Guarantees2017
- STL⁎: Extending signal temporal logic with signal-value freezing operatorInformation and Computation, 2014
- S-TaLiRo: A Tool for Temporal Logic Falsification for Hybrid Systems2011
- Breach, A Toolbox for Verification and Parameter Synthesis of Hybrid Systems2010
- Robustness of temporal logic specifications for continuous-time signalsTheoretical Computer Science, 2009
- Specifying real-time properties with metric temporal logicReal-Time Systems, 1990