Lightweight and Trust-Aware Routing in NoC-Based SoCs
Authors:
- 1 July 2020
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 160-167
Abstract
Increasing System-on-Chip (SoC) design complexity coupled with time-to-market constraints have motivated manufacturers to integrate several third-party Intellectual Property (IP) cores in their SoC designs. IPs acquired from potentially untrusted vendors can be a serious threat to the trusted IPs when they are connected using the same Network-on-Chip (NoC). For example, the malicious IPs can tamper packets as well as degrade SoC performance by launching DoS attacks. While existing authentication schemes can check the data integrity of packets, it can introduce unacceptable overhead on resource-constrained SoCs. In this paper, we propose a lightweight and trust-aware routing mechanism to bypass malicious IPs during packet transfers. This reduces the number of re-transmissions due to tampered data, minimizes DoS attack risk, and as a result, improves SoC performance even in the presence of malicious IPs. Experimental results demonstrate significant improvement in both performance and energy efficiency with minor impact on area overhead.Keywords
This publication has 23 references indexed in Scilit:
- Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip2017
- Hardware IP Security and Trust2017
- Secure Model Checkers for Network-on-Chip (NoC) Architectures2016
- Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip2015
- SurfNoC2013
- A Security Framework for NoC Using Authenticated Encryption and Session KeysCircuits, Systems, and Signal Processing, 2013
- The gem5 simulatorACM SIGARCH Computer Architecture News, 2011
- McPAT2009
- DyXY2006
- Analysis of error recovery schemes for networks on chipsIEEE Design & Test of Computers, 2005