A low-jitter mixed-mode DLL for high-speed DRAM applications
Authors:
- Jae Joon KimJKJae Joon Kim
- Sang-Bo LeeSLSang-Bo Lee
- Tae-Sung JungTJTae-Sung Jung
- Chang-Hyun KimCKChang-Hyun Kim
- Soo-In ChoSCSoo-In Cho
- Beomsup KimBKBeomsup Kim
- 1 October 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 35 (10) , 1430-1436
Abstract
This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-/spl mu/m triple-metal CMOS process and occupies a die area of 0.45 mm/sup 2/. Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply.Keywords
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