Accelerating video and image processing design for FPGA using HDL coder and simulink
Authors:
- 1 October 2015
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-5
Abstract
Video and Image Processing solution requiring high throughput rate are often implemented in a dedicated hardware such as FPGA. The design process traditionally uses Verilog and VHDL for synthesizing and validating the hardware. These design process are technically complex and time consuming. In this paper, we present an alternative approach using a model based design framework based on HDL Coder, Vision HDL Toolbox and Simulink to accelerate the design of video and image solution. Several important issues in this framework are discussed namely, Pixel Streaming Design, Co-simulation and FPGA in the Loop (FIL). Based on this framework, a video of human walking are processed to extract out two features which are the human height and edge. The design is implemented in an Altera DE2-115 FPGA board. The goal of this paper is to tackle the technical complexity and reduce development time of traditional FPGA design.Keywords
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