Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods
Authors:
- U. KrautzUKU. Krautz
- M. PflanzMPM. Pflanz
- C. JacobiCJC. Jacobi
- H.W. TastHTH.W. Tast
- K. WeberKWK. Weber
- H.T. VierhausHVH.T. Vierhaus
- 1 January 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1 (15301591) , 1-6
Abstract
In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designsKeywords
This publication has 13 references indexed in Scilit:
- Soft Errors in Advanced Computer SystemsIEEE Design & Test of Computers, 2005
- Automatic Formal Verification of Fused-Multiply-Add FPUs2005
- Fault injection for verifying testability at the VHDL level2004
- Event-centric simulation of crosstalk pulse faults in sequential circuits2004
- Online Fehler-Erkennung und schnelle Wiederherstellungs-Techniken für zuverlässige eingebettete Prozessoren (Online Error Detection and Fast Recover Techniques for Dependable Embedded Processors)it - Information Technology, 2004
- Experimental evaluation of error-detection mechanismsIEEE Transactions on Reliability, 2003
- A comparison of simulation based and scan chain implemented fault injection2002
- On-line error detection techniques for dependable embedded processors with high complexity2002
- Validating fault tolerant designs using laser fault injection (LFI)1997
- An SFS Berger check prediction ALU and its application to self-checking processor designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992