2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter
- 26 October 2020
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 56 (7) , 2007-2017
Abstract
High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2x compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm². It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.Keywords
Funding Information
- Analog Devices
This publication has 20 references indexed in Scilit:
- 24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications2017
- A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching NetworkIEEE Journal of Solid-State Circuits, 2017
- A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal Noise CancellationIEEE Journal of Solid-State Circuits, 2015
- A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 CalibrationIEEE Journal of Solid-State Circuits, 2014
- SAW-Less Analog Front-End Receivers for TDD and FDDIEEE Journal of Solid-State Circuits, 2013
- A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure2012
- Tunable High-Q N-Path Band-Pass Filters: Modeling and VerificationIEEE Journal of Solid-State Circuits, 2011
- A 2-dB noise figure 900-MHz differential CMOS LNAIEEE Journal of Solid-State Circuits, 2001
- A 1.5-V, 1.5-GHz CMOS low noise amplifierIEEE Journal of Solid-State Circuits, 1997
- Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOSIEEE Journal of Solid-State Circuits, 1995