Effects of Junction Capacitances and Commutation Loops Associated With Line-Frequency Devices in Three-Level AC/DC Converters

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well-known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shape and I-shape three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a Gallium nitride (GaN) based 115 $V_{ac}/650 V_{dc}/1.5$ kW/450 kHz Vienna-type rectifier and a SiC MOSFET based 1 kV/10 kW/280 kHz three-level (3L) active neutral-point-clamped (ANPC) inverter confirm the presented effects and verify the associated analysis and solutions.