A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation

Ring-oscillator (RO)-based digital PLLs (DPLLs) are well-suited for multi-PLL -integrated SoC designs owing to their compactness and immunity to magnetic coupling. However, their inferior phase noise (PN) limits their utilization in low-jitter applications. To tackle this, both the quantization noise (Q-noise) and RO PN $(\mathsf{PN}_{\mathsf{R}0})$ need to be well suppressed. Previous techniques reported in the literature to address these limitations are often prone to process, voltage, and temperature (PVT) variations or are energy inefficient. Figure 19.1.1 reviews popular PN-quantization and $\mathsf{PN}_{\mathsf{R}0}$ -suppression schemes. The classic time-to-digital-converter (TDC) scheme suffers from high Q-noise due to the technology-limited delay (T) and simultaneously hig $\mathsf{h} \ T$ variation over PVT, thus significantly compromising the PN performance and loop stability. Alternatively, the optimal-threshold-TDC (OT-TDC) scheme [1], [2] can achieve ultra-low Q-noise, which in turn necessitates a statistical-based background calibration for threshold delays $(+T_{\mathsf{U}}$ and $-T_{\mathrm{L}})$. Similarly, for the $\mathsf{PN}_{\mathsf{R}0}$ suppression, the fast phase-error correction (FPEC) [1], [2] is as effective as the phase realignment. However, its phase-correction gain (K-gain) requires correlation-based background calibration. The cascaded RO-PLL [3] offers a PVT-stable $\mathsf{PN}_{\mathsf{R}02}$ suppression but relies on a high-frequency and low-PN PLL 1 with a power-consuming R01. This work presents a low-jitter fractional-N cascaded RO-DPLL that leverages the time-to-voltage converter (TVC) and analog-to-digital converter (ADC) to retain a PVT-robust and low-Q-noise PN quantization. It simultaneously facilitates a voltage-domain feedforward noise cancellation (V-FFNC), removing the need for gain calibration and consuming low power. A self-reference-generation scheme enables a fast restoration of the cancellation gain of a delta-sigma-modulator (DSM) Q-noise during the fractional-frequency-control word $(\mathsf{FCW}_{\mathsf{F}})$ transitions. The prototype RO-DPLL achieves 290.8fs rms jitter and -62dBc worst fractional spurs at an output frequency near 5.5GHz. With -20-to-1 OO°C-temperature and $\pm$ 5%-supply-voltage $(V_{\mathsf{DD}})$ variations, the measured jitter deviations remain within 7.5%.