Towards Interdisciplinary Energy-Efficient Computing for the Post-Transistor Scaling Era

Authors:
  • GPGregory D Peterson
    Gregory D Peterson
  • CHCheol-Ho Hong
    Cheol-Ho Hong
  • LMLev Mukhanov
    Lev Mukhanov
  • ITIoannis Tsiokanos
    Ioannis Tsiokanos
  • XZXiaojun Zhai
    Xiaojun Zhai
  • HMHaralambos Mouratidis
    Haralambos Mouratidis
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Abstract
In the post-transistor scaling era, defined in this paper as the era in which further reductions in operational voltage and capacitance by shrinking transistor size are no longer achievable, architectural optimizations alone become insufficient, necessitating the interdisciplinary optimizations including Algorithmic, Arithmetic, and Architectural optimizations (3A optimizations). To the best of our knowledge, no unified framework exists that captures the interactions of such cross-discipline optimizations and their collective impact on energy efficiency. Therefore, we propose such a unified framework that explains how interdisciplinary 3A optimizations interact and contribute to overall energy efficiency. To develop the framework, we introduce a new energy-efficiency metric, Transistor Arithmetic Density (TAD), defined as the arithmetic density per transistor toggling activity. We conclude that energy-efficient computing strategies in the post scaling era should focus on improving the two key components, operational efficiency and TAD, without affecting accuracy and stability of the algorithm.