A realistic fault simulation model for EEPROM memories
Authors:
- 1 November 2009
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
Abstract
In this paper, a list of faults is injected in an elementary memory array circuit. Electrical simulation results show impact of each fault on EEPROM cells logical values and threshold voltages. Results are analyzed and fault coverage of EEPROM memories standard test patterns is evaluated.Keywords
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