Rachid Beguenane

This paper presents the modeling, rapid control prototyping, and hardware-in-the-loop testing for real-time simulation and control of a grid-connected doubly fed induction generator (DFIG) in a laboratory-size wind turbine emulator for wind energy conversation systems. The generator is modeled using the direct-quadrature rotating reference frame circuit along with the aligned stator flux, and the field-oriented control approach is applied for independent control of the active and reactive power and the DC-link voltage at the grid side. The control of the active, reactive power and the DC-link voltage are performed using a back-to-back converter at sub- and super-synchronous as well as at variable speeds. The control strategy is experimentally validated on an emulated wind turbine driven by the Opal-RT real-time simulator (OP5600) for simultaneous control of the DC-link voltage, active and reactive power.

An automatic power management system, to monitor the distribution of power to a set of load banks, is presented in this paper. The required power is generated from a laboratory-size pitch-controlled wind turbine experimental workstation. The management system is a sequence of logic expressions, based on the generated power, a profile of the banks’ states provided by the supervisor and the banks’ priorities, to obtain an optimal behavior of the system and to ensure the load requirement. A modified PI pitch angle control is proposed to regulate the generated power for tracking the power reference in order to maintain a consistent brilliance of the load’s LEDs, to reduce the activity of the pitch actuator and to deal with fluctuation problems. Experimental results are provided to show the effectiveness of the proposed automatic power management system for load banks supplied by a pitch controlled wind turbine.

This paper proposes a method of implementing parallel gene prediction algorithms in MATLAB. The proposed designs are based on either Goertzel’s algorithm or on FFTs and have been implemented using varying amounts of parallelism on a central processing unit (CPU) and on a graphics processing unit (GPU).