Hiroshi Tsuji

We have fabricated poly-silicon-based thin film transistors (TFTs) on glass substrates, and achieved ultra-low power consumption by driving at 1 V. The gate oxide layer has a 10 nm thick stacked structure with a 1.4 nm interfacial SiO₂ layer formed by the nitric acid oxidation of silicon (NAOS) method and a 8.6 nm SiO₂ layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. The dynamic power consumption ratio of the NAOS-TFTs is 1/144 of that for the currently commercial TFTs with the driving voltage of 12 V and 80 nm gate oxide. The off-current decreases by ∼2 orders of magnitude by insertion of the ultra-thin NAOS SiO₂ layer. The off-current decrease is attributed to i) blocking of the gate leakage current by the NAOS SiO₂ layer, and ii) improvement of the quality of the deposited oxide on the NAOS SiO₂ layer because of better nucleation, and consequently, the high on/off ration exceeding 10⁹ is achieved.

The luminescence properties from shallowly Ge-implanted SiO 2 layer were investigated for the purpose of fabrication of optical light source in blue-UV range at very low voltage operation. Germanium negative ions were implanted into 50-nm SiO 2 layer on Si at very shallow depth from the surface to several tens nm at 10-50 keV and different incident angles. After post annealing, we measured photoluminescence and electroluminescence properties. We have obtained PL peaks at 290 nm and 390 nm in wavelength. In the EL measurement by applying AC voltage between the comb-shape transparent ITO electrode deposited on the SiO 2 surface and the Al electrode on Si rear side, the considerably strong EL peak was obtained at around 390 nm in wavelength at AC 20 volts.

We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain current-voltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 12-15 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

The cathodeluminescencs (CL), photoluminescence (PL), and electroluminescence (EL) properties of Ge implanted SiO₂ films (SiO₂:Ge) were investigated. The SiO₂ films on Si substrate were implanted with Ge-negative ions. The implanted Ge atom concentrations in the films were 3 and 6 at. %. Ge nanoparticles were formed in the SiO₂ films after annealing. CL, PL and EL were observed at wavelengths around 400 nm from the SiO₂:Ge films. CL of GeO₂ films were also investigated. The CL intensity from the GeO₂ films is obviously lower than that from the SiO₂:Ge films with 6 at.% of Ge atomic concentration. Strong EL from large area of the films was not only to be easily seen with naked eye but also to be measured its wavelength. Ooperating voltage was an order of magnitude lower and the emitting area was two orders of larger than those reported previously. These results suggested that annealing of SiO₂:Ge films in moderate oxidative atmosphere is suitable method for the strong luminescence due to Ge-related oxygen deficient center (Ge-ODC).

Ge nanoparticles (NPs) embedded silicon oxide is expected to be promising light emission source, especially, UV – blue light region. We have tried to form Ge NPs in a 100- nm-thick SiO2 layer on Si substrate by multi-energy implantation of Ge negative ions with energies of 50, 20 and 10 keV and doses of 1.4 × 1016, 3.2 × 1015 and 2.2 × 1015 ions/cm², respectively. Samples were annealed for 1 h at a temperature less than 900oC. By this implantation, Formations of Ge nanoparticles in a surface 50-nm depth region were expected. The depth distribution of implanted Ge atoms in the oxide was measured by XPS (Ge 2p, O 1s, Si 2p) with monochromatic Al K.. and Ar etching at 4 keV. The depth profiles were well agreed with the cross-sectional TEM image. But some extent of Ge atoms diffused to the SiO2/Si interface at 900 oC. The chemical sifted spectra of Ge 2p3/2 showed about 60 % of the oxidation of Ge atom around the end of the range (EOR) even in the as-implanted sample. This oxidation was considered to be due to the excess oxygen atoms near EOR by forward of sputtered oxygen atoms from SiO2 layer. Raman spectra supported this oxidation. In a preliminary investigation of cathode luminescence, the Ge-implanted sample with annealing at 600oC showed CL peak at 3.12 eV (397 nm in wavelength) in UV-blue region at room temperature. This means the Ge-implanted sample has a possibility for light emission in the UV-blue region.

We implanted germanium negative ions into a 100-nm-thick SiO2 layer on Silicon substrate and have investigated about oxidation of implanted Ge atoms and cathode luminescence for the possibility of blue light emission. The ions were implanted into the same SiO2 layer with three times at different energies of 50, 20, and 10 keV (multi-energy implantation). The dose amounts were 1.4 x 10^16, 3.2 x 10^15 and 2.2 x 10^15 ions/cm2, respectively. Samples were annealed for 1 h at a temperature less than 900°C. The depth distribution and oxidation of implanted Ge atoms in the oxide were measured by XPS analysis with Ar etching. The depth profiles were well agreed with the cross-sectional TEM image. But some extent of Ge atoms diffused to the SiO2/Si interface at 900 °C. The chemical sifted spectra of Ge 2p3/2 showed about 60 % of the oxidation of Ge atom around the end of the range (EOR) even in the as-implanted sample. This oxidation was considered to be due to the excess oxygen atoms near EOR by forward of sputtered oxygen atoms from SiO2 layer. In cathode luminescence measurement, the Ge-implanted sample after annealing at 800°C showed strongest CL peak at 3.12 eV (397 nm in wavelength) in UV-blue region at room temperature. This means the Ge-implanted sample has a possibility for light emission in the UV-blue region.

We have investigated about limitation of line width in surface modification of polystyrene for nerve cell adhesion and neurite outgrowth by carbon negative-ion implantation. Carbon negative ions were implanted into polystyrene film on glass at 10 keV with 3 x 10^15 ions/cm^2 through a double-mask set with array of ridge shaped apertures gradually changing the width from 50 to 0 nm. The polystyrene film was prepared three times by spin coating with 7% PS in toluene at a speed of 1,000 rpm. After seeding on the modified SCPS sample, nerve-like cells of PC-12h were cultured with DMEM medium including 10% serum for 2 days in an incubator with 5%CO2 air flow at 37°C. Then, the cells were cultured for more 2 days in the incubator after replacing the serum DMEM medium to serum-free DMEM. As a result, the cell body adhered on the ion implanted area with the minimum width of 7 nm, and neurite outgrowth was observed also observed only on the ion implanted area m1til the width of 5 nm.