Chadwin D. Young

SiO ₂ and HfO ₂ > gate dielectrics with TiN electrodes were subjected to an aggressive post-fabrication plasma exposure. A comparison of plate and comb antenna structures before and after exposure demonstrated that the plate antennae structures demonstrate evidence of plasma-induced damage while the comb structures did not. The physical origin of PD in SiO ₂ devices was found to be the amphoteric interface states, while the primary effect in HfO ₂ devices was charges trapped in the bulk of the high-K film.

Using a combination of electrical characterization techniques, one can separate contributions from generated and pre-existing electron traps inherent to high-k dielectrics, as well as identify process-induced effects in the device characteristics

High-k gate stack reliability has become one of the critical factors impacting the introduction of advanced gate stacks in future technology nodes. A high density of as-grown electron traps in the transition metal oxides (Bersuker et al., 2004) and the presence of the SiO ₂ layer at the interface between the high-k dielectric and the substrate, complicate evaluation of stress-induced defect generation in high-k gate stacks (Lee et al., 2005), (Ribes et al., 2005). Effectiveness of stress-induced trap generation in high-k dielectrics remains a controversial issue, with the conclusions varying with the applied techniques and test conditions (Bersuker et al., 2004)-(Huo et al., 2004). Thus, there is a strong need to de-convolute the contributions to trap generation from the interfacial Si O ₂ layer (IL) and high-k film (Degraeve et al., 2003). In this study, by using a set of gate stacks with various combinations of the high-k film and ILs thicknesses, and a developed analysis methodology for charge pumping (CP) data, we identified the IL in the stack as the potential reliability "weak link"

Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO ₂ /HfO ₂ /TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO ₂ layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO ₂ layer. These results point to the IL as a major focus for reliability improvement of high-k stacks

Using a combination of electrical characterization techniques, one can separate contributions from generated and pre-existing electron traps inherent to high-k dielectrics, as well as identify process-induced effects in the device characteristics