Hamed Aminzadeh

On‐chip resistors are susceptible to temperature variations, affecting the performance of linear voltage‐to‐current (VI) conversion and vice versa. This paper introduces an approach to implement resistive networks that are highly immune to temperature variations across a wide range by combining complementary‐to‐absolute‐temperature (CTAT) and proportional‐to‐absolute‐temperature (PTAT) resistors existing in standard CMOS technology. The proposed resistive networks, aiming for linear VI conversion in voltage and current references (VCRs), yield ultra‐low temperature coefficient (TC). Optimization is carried out using a multi‐objective heuristic algorithm to find the optimal placement, TC and sizes of the elements within the final configuration. Post‐layout simulation results in a standard 0.18‐μm CMOS process demonstrate the possibility of implementing sub‐3 ppm/°C resistors across −40 ~ 120°C temperature range, improving the prior art by more than 5×. A modern VCR configuration is implemented based on the proposed methodology, and simulation results verify the effectiveness of the modified approach in improving the accuracy of VI conversion.

This paper presents Hybrid Cascode Compensation with Hybrid Q –Factor Control (HCCHQ), for three-stage feedback operational transconductance amplifiers (OTA) capable of handling any load capacitor ( C_L ). The design incorporates an enhanced Miller compensation strategy, exploiting cascode-Miller compensation with hybrid pathways to effectively separate the dominant pole from non-dominant poles for bandwidth expansion. It also combines a hybrid quality factor ( Q –factor) control with a local impedance attenuation (LIA) module, adjusting the Q –factor of non-dominant poles by mitigating the ringing in the time response and the frequency peaking for lighter C_Ls . The new design can accommodate capacitive loads ranging from zero to infinity, owing to the Miller– and load–compensated solutions for the light and heavy C_Ls , respectively. Fabricated in a 180-nm standard CMOS process, a prototype of the proposed amplifier demonstrates a quiescent current of 25 μA under a 1.8 V single supply. It boasts a compact 0.0055 mm ² area and exhibits unconditional stability when configured as a voltage buffer driving any C_L . With a mean DC gain of 115 dB, the average unit-gain frequency (UGF) is 2.30 MHz and 0.11 MHz for 0.1 and 47 nF external capacitive loads, respectively. The mean 1% settling time is measured as 2.41 μs and 40 μs for the same capacitive loads, respectively, when a 0.4 V pulse signal is applied to the input.

Summary: Maintaining proper current sharing among distributed generation (DG) units while regulating the output voltage is a challenging control issue in DC microgrids. The conventional droop control is widely used at the primary level of control to tackle this issue, but this method faces some limitations in voltage control and current sharing. To address this problem, this paper presents a new distributed secondary control method that determines the resistance of transmission lines by injecting an external pulse to the reference voltage of each converter and measuring output voltage and current changes. The proposed secondary control signal, denoted as , enables simultaneous proportional current sharing and voltage restoration in the DC microgrid by correcting the droop coefficients based on the determined resistances. In order to ensure the stability of the proposed method, the small signal stability analysis of the closed‐loop system is conducted, considering various parameter changes. In contrast to similar methods, the proposed method introduces a new hybrid technique of voltage setpoint shifting and droop parameter adjustment that achieves precise proportional current sharing and voltage restoration, even when faced with varying resistive loads and constant power loads (CPLs). Additionally, the proposed method demonstrates outstanding characteristics, such as high convergence speed, the ability to determine transmission line resistances instead of assuming them to be known, and robustness in plug‐and‐play scenarios and communication system failures. The simulation results in MATLAB and experimental tests confirm the effectiveness of the proposed method.

Different winner-take-all (WTA) and loser-take-all (LTA) circuits are studied, and their operations are analyzed in this review. The exclusive operation of the current conveyor, binary tree, and time-domain WTA/LTA architectures, as the most important architectures reported in the literature, are compared from the perspectives of power consumption, speed, and precision.

Feedback amplifiers consisting of multiple gain stages are used to establish highly accurate buffered/amplified signals that can drive a wide range of capacitive load (CL). This article models, analyzes, and presents the measurement results of a high-gain four-stage operational transconductance amplifier (OTA) that is able to handle a wide range of CL up to infinity. In addition to local compensation capacitors and nulling resistors in the intermediate stages, two high-speed feedback loops made by parallel Miller capacitors and current buffers provide Miller compensation and the consequent pole-splitting in the lower CL range. The dominant pole is made dependent on the CL for the higher CL range, enabling the maintenance of the stability conditions up to infinite CL. The proposed amplifier was integrated into a 65-nm CMOS technology, consuming 140- $\mu \text{A}$ static current under a 1.2-V supply and an active area of 0.0086 mm2. A dc gain greater than 100 dB was also perceived with a unity-gain frequency (UGF) of 4.09, 2.01, and 0.27 MHz for 4.7, 10, and 100-nF load capacitors, respectively. The average slew rate (SR) is 0.59 V/ $\mu \text{s}$ , when the OTA is formed as a buffer targeting the CLs higher than 4.7-nF.

A simple yet effective approach to improve the linearity of the transconductor-capacitor ( G_m-C ) filters is proposed without any area or power overhead. Following a generalized nodal analysis, the transconductors of classical filter topology are rewired such that their input differential voltage lies within the linear regime. The effectiveness of the proposed method is validated through the design and simulation of a fifth-order Butterworth low-pass filter (LPF) in a standard 65-nm CMOS process. The proposed filter implementation occupies 0.0164 mm ² (0.003 mm ² /pole) die area and consumes 167-μW for the cut-off frequency of 1-MHz. Operating at 1-V voltage supply, it shows an in-band total harmonic distortion (THD) of –49.14 dB for 200-mV peak-to-peak 1MHz differential voltage. An in-band 3rd-order intercept point (IIP3) of 9.36 dBm is also achieved with an in-band spurious-free-dynamic range (SFDR) greater than 53-dB, all of which reflect meaningful improvements relative to the classical architecture and despite the modest linearity performance of the internal G_m stages.

This paper presents an ultra-low-power voice activity detection (VAD) system to discriminate speech from non-speech parts of audio signals. The proposed VAD system uses level-crossing sampling for voice activity detection. The useless samples in the non-speech parts of the signal are eliminated due to the activity-dependent nature of this sampling scheme. A 40 ms moving window with a 30 ms overlap is exploited as a feature extraction block, within which the output samples of the level-crossing analog-to-digital converter (LC-ADC) are counted as the feature. The only variable used to distinguish speech and non-speech segments in the audio input signal is the number of LC-ADC output samples within a time window. The proposed system achieves an average of 91.02% speech hit rate and 82.64% non-speech hit rate over 12 noise types at −5, 0, 5, and 10 dB signal-to-noise ratios (SNR) over the TIMIT database. The proposed system including LC-ADC, feature extraction, and classification circuits was designed in 0.18 µm CMOS technology. Post-layout simulation results show a power consumption of 394.6 nW with a silicon area of 0.044 mm², which makes it suitable as an always-on device in an automatic speech recognition system.