Ezz El-Masry

Photo-voltaic (PV) power harvest can have decent efficiency when dealing with high power. When operating with a DC–DC boost converter during the low-power harvest, its efficiency and output voltage are degraded due to excessive losses in the converter components. The objective of this paper is to present a systematic approach to designing an efficient low-power photo-voltaic harvesting topology with an improved efficiency and output voltage. The proposed topology uses a boost converter with and extra inductor in recycled and synchro-recycled techniques in continuous current mode (CCM). By exploiting the non-linearity of the PV cell, it reduces the power loss and using the current stored in the second inductor, it enhances the output voltage and output power simultaneously. Further, by utilizing the Metal Oxide Silicon Field Effect Transistor’s (MOSFET) body diode as a switch, it maintains a minimum hardware, and introduces a negligible impact on the reliability. The test results of the proposed boost converters show that it achieves a decent power and output voltage. Theoretical and experimental results of the proposed topologies with a tested prototype are presented along with a strategy to maximize power and voltage conversion efficiencies and output voltage.

A distortion-compensated charge transfer amplifier (DCCTA) is proposed to improve the linearity constraints of the differential charge transfer amplifier (DCTA). The proposed DCCTA effectively reduces distortion at its output by source degeneration, cross coupling, and making the drain-to-source voltage of the amplifying transistor independent of the applied input signal. This DCCTA yields an effective number of bits of 9.26 bits, compared with 6.05 bits for the DCTA at 40 MHz while consuming only 13.5 μW from a 1.2-V source. A 1.66-MHz cyclic pipeline analog-to-digital converter employing this DCCTA as a residue amplifier was simulated using 90-nm CMOS process, resulting in a peak resolution of 9.21 bits, without being limited by the thermal noise.

This paper presents extensive simulations of MEMS parallel plate variable capacitors with attention dedicated towards variations in etching holes' properties. For various separation distances between the plates, different hole sizes and density were created and capacitances were extracted. Within typical values, it was found that the configuration of the holes might affect the tuning range by no more than 16% at extreme cases of their theoretical counterparts. Simulations were done using finite element modeling

A current mirror circuit that uses body-driven MOSFETs to achieve an ultra-low input and output voltage is presented. High-gain amplifiers, suitable for a deep submicron process, are used to provide matching as well as input and output regulation. Simulation results were verified with measurements performed on a fabricated chip using the 90-nm CMOS process from ST-Microelectronics.