Simon Schliecker
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Simon Schliecker has a total of 12 co-authors. Here are the top co-authors by number of shared publications:
- Rolf Ernst
Institute of Computer and Network Engineering, Technische Universitt Braunschweig, Braunschweig, Germany
5 shared publications - Matthias Ivers
Technical University of Braunschweig, Germany
2 shared publications - Arne Hamann
Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Braunschweig, Germany
1 shared publication - Ernesto Wandeler
ETH Zurich
1 shared publication - Jonas Rox
Institute of Computer and Communication Network Engineering, Technische Universität Braunschweig, Braunschweig, Germany
1 shared publication - Lothar Thiele
ETH Zurich Switzerland
1 shared publication
Latest Publications
- 27 October 2011
- Published by Springer Nature
- p. 171-189
System Level Performance Analysis for Real-Time Multi-Core and Network Architectures
- 27 October 2011
- Published by Springer Nature
- p. 171-189
System Level Performance Analysis for Real-Time Multi-Core and Network Architectures
- 26 April 2008
- Published by Springer Nature in Design Automation for Embedded Systems
- Vol. 13 (1-2) , 27-49
Influence of different abstractions on the performance analysis of distributed hard real-time systems
- 26 April 2008
- Published by Springer Nature in Design Automation for Embedded Systems
- Vol. 13 (1-2) , 27-49
Influence of different abstractions on the performance analysis of distributed hard real-time systems
- 1 April 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis
In this paper we integrate two established approaches to formal multiprocessor performance analysis, namely synchronous dataflow graphs and compositional performance analysis. Both make different trade-offs between precision and applicability. We show how the strengths of both can be combined to achieve a very precise and adaptive model. We couple these models of completely different paradigms by relying on load descriptions of event streams. The results show a superior performance analysis quality
- 1 April 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis
In this paper we integrate two established approaches to formal multiprocessor performance analysis, namely synchronous dataflow graphs and compositional performance analysis. Both make different trade-offs between precision and applicability. We show how the strengths of both can be combined to achieve a very precise and adaptive model. We couple these models of completely different paradigms by relying on load descriptions of event streams. The results show a superior performance analysis quality
- Open Access
- 22 October 2006
- Published by Association for Computing Machinery (ACM)
- p. 288-293
Integrated analysis of communicating tasks in MPSoCs
- 22 October 2006
- Published by Association for Computing Machinery (ACM)
- p. 288-293
Open AccessIntegrated analysis of communicating tasks in MPSoCs
- 1 June 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 249-252
Memory Access Patterns for the Analysis of MPSoCs
Unlike distributed systems, multiprocessor systems-on-chip often cannot integrate all memory needed for high performance applications within each processor. Hence, accesses to instruction and data memory use the same communication infrastructure as communication between processes. In this paper, we give an overview on an approach to analyze system timing in the presence of memory and coprocessor accesses in MpSoC systems and present a method to derive safe bounds on the traffic generated by tasks as well as resources with multiple tasks mapped to it
- 1 June 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 249-252
Memory Access Patterns for the Analysis of MPSoCs
Unlike distributed systems, multiprocessor systems-on-chip often cannot integrate all memory needed for high performance applications within each processor. Hence, accesses to instruction and data memory use the same communication infrastructure as communication between processes. In this paper, we give an overview on an approach to analyze system timing in the presence of memory and coprocessor accesses in MpSoC systems and present a method to derive safe bounds on the traffic generated by tasks as well as resources with multiple tasks mapped to it