Mostafa Kishani

Low-latency Vehicular Edge Computing (VEC) applications require an efficient VEC resource allocation considering all components contributing to application latency, i.e., computation, communication, and storage. While the optimization of communication and computation resources is broadly addressed in literature, storage, a significant source of latency in the computing stack, is often ignored in existing works. Thus, in this paper, we optimize the communication and computation resources together with the storage resources to minimize the latency of VEC applications. The problem of jointly minimizing communication, computation, and storage latency under practical constraints is NP-hard. Hence, we employ dual decomposition and Lagrangian relaxation to achieve a computationally viable solution for the joint communication, computing, and storage resource allocation to VEC applications. To this end, we define a dual problem of the assignment of VEC applications to base stations. This problem corresponds to the perfect matching problem in a weighted bipartite graph and optimally solvable by algorithms with polynomial computation complexity. Then, as the solution to the dual problem may violate some constraints of the main resource allocation problem, we find a feasible solution to the main resource allocation problem using Lagrangian relaxation. We show that the joint optimization of all three aspects, i.e., communication, computation, and storage, reduces the overall offloading latency up to 60% compared to state-of-the-art works.

Hyperconverged Infrastructures (HCIs) combine processing and storage elements to meet the requirements of data-intensive applications in performance, scalability, and quality of service. As an emerging paradigm, HCI should couple with a variety of traditional performance improvement approaches such as I/O caching in virtualized platforms. Contemporary I/O caching schemes are optimized for traditional single-node storage architectures and suffer from two major shortcomings for multi-node architectures: a) imbalanced cache space requirement and b) imbalanced I/O traffic and load. This makes existing schemes inefficient in distributing cache resources over an array of separate physical nodes. In this paper, we propose an Efficient and Load Balanced I/O Cache Architecture (ELICA), managing the solid-state drive (SSD) cache resources across HCI nodes to enhance I/O performance. ELICA dynamically reconfigures and distributes the SSD cache resources throughout the array of HCI nodes and also balances the network traffic and I/O cache load by dynamic reallocation of cache resources. To maximize the performance, we further present an optimization problem defined by Integer Linear Programming to efficiently distribute cache resources and balance the network traffic and I/O cache relocations. Our experimental results on a real platform show that ELICA improves quality of service in terms of average and worst-case latency in HCIs by 3.1× and 23%, respectively, compared to the state-of-the-art.

The latency associated with accessing data stored on edge computing servers for vehicles encompasses both the communication between a vehicle and a server as well as a latency of a data storage system. To enable low-latency vehicular services, an efficient resource management should consider the communication as well as the storage I/O cache resource allocation along with a data access pattern and a priority of individual vehicular services. Therefore, we focus on a joint optimization of communication and storage I/O cache resource allocation for access to data of vehicular services hosted by the edge computing servers. The proposed framework determines the data placement for the services and allocates communication and storage I/O cache resources to each service. The objective is to minimize the overall latency experienced by vehicular services for access to data. The edge computing platforms share storage and communication resources among various vehicular services, each having distinct priorities and data access rates or patterns. Hence, to reflect different priorities of services in resource allocation, our objective metric takes into account the service priority, data access frequency, and latency. We propose a feasible solution using dual relaxation considering both communication and storage latencies. The proposed solution reduces the average latency of vehicular services by up to 1.8x compared to the state-of-the-art resource allocation method for vehicular edge computing. Even more notable improvement is observed for high priority vehicular services, where the proposal leads to 2.5x lower latency compared to the state-of-the-art storage I/O cache architecture for virtualized cloud services.

Emergence of Solid-State Drives (SSDs) have evolved the data storage industry where they are rapidly replacing Hard Disk Drives (HDDs) due to their superiority in performance and power. Meanwhile, SSDs have reliability issues due to bit errors, bad blocks, and bad chips. To help reliability, Redundant Array of Independent Disks (RAID) configurations, originally proposed to increase both performance and reliability of HDDs, are also applied to SSD arrays. However, the conventional reliability models of HDD RAID cannot be intactly applied to SSD arrays, as the nature of failures in SSDs are totally different from HDDs. Previous studies on the reliability of SSD arrays are based on the deprecated SSD failure data, and only focus on limited failure types, device failures, and page failures caused by the bit errors, while recent field studies have reported other failure types including bad blocks and bad chips, and a high correlation between failures. In this paper, we investigate the reliability of SSD arrays using field storage traces and real-system implementation of conventional and emerging erasure codes. The reliability is evaluated by statistical fault injection experiments that post-process the usage logs obtained from the real-system implementation, while the fault/failure attributes are obtained from the state-of-the-art field data by previous works. As a case study, we examine conventional RAID5 and RAID6 and emerging Partial-MDS (PMDS) codes, Sector-Disk (SD) codes, and STAIR codes in terms of both reliability and performance using an open-source software RAID controller, MD (in Linux kernel version 3.10.0-327), and arrays of Samsung 850 Pro SSDs. Our detailed analysis on the data loss breakdown shows that a) emerging erasure codes fail to replace RAID6 in terms of reliability, b) row-wise erasure codes are the most efficient choices for contemporary SSD devices, and c) previous models overestimate the SSD array reliability by up to six orders of magnitude, as they just focus on the coincidence of bad pages (bit errors) and bad chips within a data stripe that holds the minority of root cause of data loss in SSD arrays. Our experiments show that the combination of bad chips with bad blocks is recognized as the major source of data loss in RAID5 and emerging codes (contributing more than 54% and 90% of data loss in RAID5 and emerging codes, respectively), while RAID6 remains robust under these failure combinations. Finally, the fault injection results reveal that SSD array reliability, as well as the failure breakdown is significantly correlated with SSD type.

In recent years, high availability and reliability of data storage systems (DSS) have been significantly threatened by soft errors occurring in storage controllers. Due to their specific functionality and hardware-software stack, error propagation and manifestation in DSS is quite different from general-purpose computing architectures. To the best of our knowledge, no previous study has examined the system-level effects of soft errors on the availability and reliability of DSS. In this paper, we first analyze the effects of soft errors occurring in the server processors of storage controllers on the entire storage system dependability. To this end, we implement the major functions of a typical data storage system controller, running on a full stack of storage system operating system, and develop a framework to perform fault injection experiments using a full system simulator. We then propose a new metric, storage system vulnerability factor (SSVF), to accurately capture the impact of soft errors in storage systems. By conducting extensive experiment, it is revealed that depending on the controller configuration, up to 40% of cache memory contains end-user data in which any unrecoverable soft errors will result in data loss (DL) in an irreversible manner. However, soft errors in the rest of cache memory filled by operating system and storage applications will result in data unavailability (DU) at the storage system level. Our analysis also shows that detectable unrecoverable errors on the cache data field are the major cause of DU in storage systems, while silent data corruptions in the cache tag and data fields are mainly the cause of DL in storage systems.

Data storage systems (DSSs) and their availability play a crucial role in contemporary datacenters. Despite using mechanisms such as automatic failover in datacenters, the role of human agents and consequently their destructive errors is inevitable. Due to very large number of disk drives used in exascale datacenters and their high failure rates, the disk subsystem in storage systems has become a major source of data unavailability (DU) and data loss (DL) initiated by human errors. In this paper, we investigate the effect of incorrect disk replacement service (IDRS) on the availability and reliability of DSSs. To this end, we analyze the consequences of IDRS in a disk array, and conduct Monte Carlo simulations to evaluate DU and DL during mission time. The proposed modeling framework can cope with different storage array configurations and data object survivability , representing the effect of system-level redundancies such as remote backups and mirrors. In the proposed framework, the model parameters are obtained from industrial and scientific reports alongside field data, which have been extracted from a datacenter operating with 70 storage racks. The results show that ignoring the impact of IDRS leads to unavailability underestimation by up to three orders of magnitude. Moreover, our study suggests that by considering the effect of human errors, the conventional beliefs about the dependability of different redundant array of independent disks (RAID) mechanisms should be revised. The results show that $\text{RAID}1$ can result in lower availability compared to $\text{RAID}5$ in the presence of human errors. The results also show that employing automatic fail-over policy (using hot spare disks) can reduce the drastic impacts of human errors by two orders of magnitude.

This work proposes an automatic method to generate optimized redundant hardware accelerator with maximum reliability given a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead.