Brahmjit Singh

Internet of Things (IoT) is marked by resource‐constrained devices. Information security is the main challenge that arises due to the wireless transmission of data by ubiquitous sensors. In this work, we have presented a lightweight advance encryption scheme (AES) that can be used in small IoT devices. Galois field arithmetic has been used to minimize the size of the S‐box. Slice consumption and throughput are two contradictory parameters in AES design. The design tries to achieve a tradeoff between these two parameters. With a separate S‐box for the key expansion, a high throughput in the range of 52–163 Mbps has been achieved on different FPGAs. In terms of throughput, it matches the latest lightweight designs and outperforms older ones. It occupies 73 slices on an Artix‐7 FPGA. When compared to existing AES designs, the design achieves area savings in the range of 4%–78.33%. In slice consumption, it is on par with most of the lightweight ciphers designed for IoT. The most remarkable feature of the design is its efficiency. It outperforms existing lightweight AES variants with a typical throughput per slice of 210 kbps/slice to 1.409 Mbps/slice. On Virtex‐5, AES‐8 has outperformed lightweight ciphers like Shadow‐64, LEA‐128, DULBC‐80/128, and QARMA. A 24%–67% resource reduction has been achieved from these ciphers. It makes the proposed cipher suitable for application in IoT security.

The most widely used asymmetric cipher is ECC. It can be applied to IoT applications to offer various security services. However, a wide range of sectors have been investigated for applying ECC. The field of elliptic curve cryptographic processors for GF (2191) has received less attention. This study presents a low-resource, high-efficiency architecture for a 191-bit ECC processor. This design uses a novel hybrid Karatsuba multiplier for the multiplication of finite fields. For GF (2191), the Quad-Itoh-Tsuji algorithm has been altered to provide a small-size inversion unit. PlanAhead software synthesizes the CPU, which is then implemented on several Xilinx FPGAs. With savings in slice consumption ranging from 16 to 43 percent, the implemented design is the most restricted compared to the current designs. Compared to previously published designs, it is 3.8–1000 times faster. The elliptic curve scalar multiplication on the Virtex-7 FPGA is computed in 7.24 μs. Additionally, the proposed design achieves savings in area-time products of 77 to 90 percent. It may be beneficial for IoT edge devices. It utilizes 3120 mW of power for the operation. A state-of-the-art comparison based on the figure of merit (FoM) reveals that the proposed design outclasses the newest designs by a large margin. It also exhibits a throughput of 138.121 Kbps.

Implementing debug logic in the SoC plays an important role before the product goes on sale. There are some design flaws and verification errors that can be found with advanced verification techniques. Because of this, it is important to add debug logic to the SoC to help with debugging. Debugging is the process of finding and fixing system errors. When silicon came out, the visibility was greatly reduced. As a result, the debug component becomes important. This task is intended to implement debug logic in the SoC. The debug infrastructure consists of debug hosts like JTAG input/output pins (TDI, TMS, TCK, TRST, TDO), protocol conversions like JTAG2APB/JTAG2AHB, and debug targets like cores. Many such protocols are needed in the VLSI industry to compete with the rapid growth of IC technology. In this work, we used the JTAG (Joint Test Action Group) protocol as the debug input pins to send the data and address to the debug target. The APB (Advanced Peripheral Bus) and AHB (Advanced High-performance Bus) protocols are used to communicate and program the debug components. JTAG2APB and JTAG2AHB act as a bridge to convert the serial communication protocol to a parallel communication protocol. As a result, we can communicate and debug any of the core. This method saves a lot of complexity in the SoC.

The evolution of wireless networks towards high mobility has led to the concept of connecting vehicles. Wireless link quality is a vital attribute of a dynamic vehicular environment and a backbone for successful communication among vehicles. The vehicles are expected to be equipped with a number of sensors and measurement devices, making a lot of data available for research. To solve the challenges in the context of the connectivity of vehicles, data-driven approaches are recently applied to estimate the dynamic attributes of vehicular networks. In this paper, a deep learning model based on an artificial neural network technique is proposed to predict wireless link quality in vehicular networks. The proposed algorithm uses the essential features, including the current location of a vehicle, to estimate the quality of a wireless link.

Background: With the availability of multiple options in wireless network simultaneously, Always Best Connected (ABC) requires dynamic selection of the best network and access technologies. Objective: In this paper, a novel dynamic access network selection algorithm based on the real time is proposed. The Available BandWidth (ABW) of each network is required to be estimated to solve the network selection problem. Methods: Proposed algorithm estimates available bandwidth by taking averages, peaks, low points and bootstrap approximation for network selection. It monitors real-time internet connection and resolves the selection issue in internet connection. The proposed algorithm is capable of adapting to prevailing network conditions in heterogeneous environment of 2G, 3G and WLAN networks without user intervention. It is implemented in temporal and spatial domains to check its robustness. Estimation error, overhead, estimation time with the varying size of traffic and reliability are used as the performance metrics. Results: Through numerical results, it is shown that the proposed algorithm’s ABW estimation based on bootstrap approximation gives improved performance in terms of estimation error (less than 20%), overhead (varies from 0.03% to 83%) and reliability (approx. 99%) with respect to existing techniques. Conclusion: Our proposed methodology of network selection criterion estimates the available bandwidth by taking averages, peaks, and low points and bootstrap approximation method (standard deviation) for the selection of network in the wireless heterogeneous environment. It monitors realtime internet connection and resolves internet connections selection issue. All the real-time usage and test results demonstrate the productivity and adequacy of available bandwidth estimation with bootstrap approximation as a practical solution for consistent correspondence among heterogeneous wireless networks by precise network selection for multimedia services.

In this article, we present an improved design of a bifrequency magnetically insulated line oscillator (BFMILO). We begin with design expressions for the output section parameters considering transmission line impedance across the extractor. This helps in proper impedance matching so as to maximize the RF power exchange arising out of the intense beam-wave interaction. In order to reproduce more RF energy from the space charge limiting current at the load, a metal plate is inserted inside the collector cavity depth. Two tapered extractor vanes are imposed at the load side along with the stub, to enhance the RF power extraction and proper RF coupling. Simulation results show that the modified collector design generates an RF output power of ~3.8 GW at dual operating frequencies, namely, 3.05 and 3.32 GHz. The peak power conversion efficiency was estimated as 16.17% with an applied voltage of 500 kV and a beam current of 47 kA.