Hyung Kook Jun
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Hyung Kook Jun has a total of 20 co-authors. Here are the top co-authors by number of shared publications:
- Won-Tae Kim
Address
4 shared publications - Young Ik Eom
Sungkyunkwan University
4 shared publications - Soo Hyung Lee
Address
3 shared publications - Young Ik Eom
Sungkyunkwan University
2 shared publications - Changwoo Min
Address
1 shared publication - Changwoo Min
Junghoon Kim, Changwoo Min, and Young Ik Eom,are with the College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Rep. of Korea
1 shared publication
Latest Publications
- Open Access
- 1 September 2025
- Published by Springer Nature in Research Square
Classification Accuracy Estimation Without Labels via Architecture-Agnostic Model Agreement
We propose a method to estimate the classification accuracy of a machine learning model without requiring any ground-truth labels, by leveraging the agreement between two models on unlabeled data. Unlike prior work that interprets model agreement as an upper bound or average of model accuracies, we are the first to demonstrate that in heterogeneous, label-free settings, agreement reliably approximates the performance of the weaker model in the pair. Our method is architecture-agnostic and does not require any labeled data, assumptions on model calibration, or prior performance information. We introduce a principled estimator that combines hard-label agreement, probability-level consistency, and a correction term for class imbalance and calibration bias. This estimator remains robust across diverse model types—including convolutional networks and Transformers—and performs reliably on standard image and text classification benchmarks. Experimental results confirm that our estimator closely approximates the accuracy of the weaker model in the pair, often within 1–2% of the ground-truth. Our approach operates entirely on in-distribution unlabeled data, offering a practical and reliable solution for model evaluation in real-world scenarios where labeled validation sets are unavailable.
- 1 September 2025
- Published by Springer Nature in Research Square
Open AccessClassification Accuracy Estimation Without Labels via Architecture-Agnostic Model Agreement
We propose a method to estimate the classification accuracy of a machine learning model without requiring any ground-truth labels, by leveraging the agreement between two models on unlabeled data. Unlike prior work that interprets model agreement as an upper bound or average of model accuracies, we are the first to demonstrate that in heterogeneous, label-free settings, agreement reliably approximates the performance of the weaker model in the pair. Our method is architecture-agnostic and does not require any labeled data, assumptions on model calibration, or prior performance information. We introduce a principled estimator that combines hard-label agreement, probability-level consistency, and a correction term for class imbalance and calibration bias. This estimator remains robust across diverse model types—including convolutional networks and Transformers—and performs reliably on standard image and text classification benchmarks. Experimental results confirm that our estimator closely approximates the accuracy of the weaker model in the pair, often within 1–2% of the ground-truth. Our approach operates entirely on in-distribution unlabeled data, offering a practical and reliable solution for model evaluation in real-world scenarios where labeled validation sets are unavailable.
- Open Access
A Hierarchical Dispatcher for Scheduling Multiple Deep Neural Networks (DNNs) on Edge Devices
This paper presents a hierarchical dispatcher architecture designed to efficiently schedule the execution of multiple deep neural networks (DNNs) on edge devices with heterogeneous processing units (PUs). The proposed architecture is applicable to systems where PUs are either integrated on a single edge device or distributed across multiple devices. We separate the dispatcher and scheduling policy. The dispatcher in our framework acts as a mechanism for allocating, executing, and managing subgraphs of DNNs across various PUs, and the scheduling policy generates optimized scheduling sequences. We formalize a hierarchical structure consisting of high-level and low-level dispatchers, which together provide scalable and flexible scheduling support for diverse DNN workloads. The high-level dispatcher oversees the partitioning and distribution of subgraphs, while the low-level dispatcher handles the execution and coordination of subgraphs on allocated PUs. This separation of responsibilities allows the architecture to efficiently manage workloads in both homogeneous and heterogeneous environments. Through case studies on edge devices, we demonstrate the practicality of the proposed architecture. By integrating appropriate scheduling policies, our approach achieves an average performance improvement of 51.6%, providing a scalable and adaptable solution for deploying deep learning models on heterogeneous edge systems.
Open AccessA Hierarchical Dispatcher for Scheduling Multiple Deep Neural Networks (DNNs) on Edge Devices
This paper presents a hierarchical dispatcher architecture designed to efficiently schedule the execution of multiple deep neural networks (DNNs) on edge devices with heterogeneous processing units (PUs). The proposed architecture is applicable to systems where PUs are either integrated on a single edge device or distributed across multiple devices. We separate the dispatcher and scheduling policy. The dispatcher in our framework acts as a mechanism for allocating, executing, and managing subgraphs of DNNs across various PUs, and the scheduling policy generates optimized scheduling sequences. We formalize a hierarchical structure consisting of high-level and low-level dispatchers, which together provide scalable and flexible scheduling support for diverse DNN workloads. The high-level dispatcher oversees the partitioning and distribution of subgraphs, while the low-level dispatcher handles the execution and coordination of subgraphs on allocated PUs. This separation of responsibilities allows the architecture to efficiently manage workloads in both homogeneous and heterogeneous environments. Through case studies on edge devices, we demonstrate the practicality of the proposed architecture. By integrating appropriate scheduling policies, our approach achieves an average performance improvement of 51.6%, providing a scalable and adaptable solution for deploying deep learning models on heterogeneous edge systems.
- 31 December 2015
- Published by Institute of Embedded Engineering of Korea in IEMEK Journal of Embedded Systems and Applications
- Vol. 10 (6) , 345-352
Interoperable Middleware Gateway Based on HLA and DDS for L-V-C Simulation Training Systems
- 31 December 2015
- Published by Institute of Embedded Engineering of Korea in IEMEK Journal of Embedded Systems and Applications
- Vol. 10 (6) , 345-352
Interoperable Middleware Gateway Based on HLA and DDS for L-V-C Simulation Training Systems
- Open Access
- 1 October 2015
- Published by Wiley in ETRI Journal
- Vol. 37 (5) , 1001-1011
Static Dalvik Bytecode Optimization for Android Applications
- 1 October 2015
- Published by Wiley in ETRI Journal
- Vol. 37 (5) , 1001-1011
Open AccessStatic Dalvik Bytecode Optimization for Android Applications
- Open Access
- 1 October 2014
- Published by Wiley in ETRI Journal
- Vol. 36 (5) , 741-751
Symbiotic Dynamic Memory Balancing for Virtual Machines in Smart TV Systems
- 1 October 2014
- Published by Wiley in ETRI Journal
- Vol. 36 (5) , 741-751
Open AccessSymbiotic Dynamic Memory Balancing for Virtual Machines in Smart TV Systems
- 8 May 2013
- Published by Springer Nature in The Journal of Supercomputing
- Vol. 66 (3) , 1613-1628
Light-weight kernel instrumentation framework using dynamic binary translation
- 8 May 2013
- Published by Springer Nature in The Journal of Supercomputing
- Vol. 66 (3) , 1613-1628
Light-weight kernel instrumentation framework using dynamic binary translation