Patrick Merken

Power autonomy is an important requirement for wireless sensor nodes. Thermoelectric generators can produce sufficient power for low power applications. Due to varying temperature, a power management circuit will be required. This paper presents such a power management circuit, realized in the AMIS I3T80 CMOS technology. It contains a Dickson charge pump with a variable number of stages as a DC/DC converter. A controller optimizes the number of stages of the charge pump, consuming 1.4 muA. The maximum efficiency of the charge pump is 82%, leading to a total efficiency that can reach up to 58%.

In the framework of the development of the European Space Agency's Herschel Space Observatory (HSO), IMEC designed the cold-readout electronics (CRE) for the PACS instrument. Key specifications for this circuit were high linearity, low power consumption, high uniformity, and very low noise at an operating temperature of 4.2K (liquid helium temperature, LHT). To ensure high production yields and uniformity, relatively easy availability of the technology, and portability of the design, the circuit was implemented in a standard CMOS technology. The circuits are functional at room temperature, which allows screening prior to integration and qualification and has an important impact on the production yield and time. The circuit was mounted on an Al₂O₃ substrate for optimum electrical performance. On the same substrate, bias signal generation, short-circuit protection circuitry, and decoupling capacitors for the power lines were integrated. This led to a relatively complex substrate containing over 30 passives and one die, integrated by means of conducting and nonconducting glue and nearly 80 wire bonds. Because the detector arrays will be cooled down to 4.2K prior to launch, reliability and launch-survivability of the mounted substrate at this temperature and in this harsh environment had to be demonstrated. For this purpose, the quality and associated reliability of every assembly step is verified during substrate mounting. This included verification of the compatibility of the bond material, optimization of the bond yield, and temperature cycling (between room temperature and LHT) of the devices. Other tests on qualification models would focus on circuit functionality under proton and gamma irradiation, cryogenic vibration tests to demonstrate launch survivability, and exhaustive temperature cycling to qualify the assembly procedure. We present in this paper the complete integration and qualification of the developed circuits, including assembly and verification during production of the flight models and qualification of the assembly method on the qualification models.

A small-size and very low-power portable electroencephalogram (EEG) acquisition system does not only improve the patients' quality of life but also extend the device applications. This paper presents a 300muW 8-channel EEG readout front-end ASIC for the implementation of portable acquisition systems. Each channel of the ASIC consists of an AC coupled chopped instrumentation amplifier, a spike filter (SF) and a variable gain stage (VGA), and achieves 80 nV/radic(Hz) input referred noise density and 130 dB CMRR at 50 Hz, while consuming 8.5 muA from a single 3V supply. ASIC has been implemented in 0.5 mum CMOS technology, core area measures 3mm by 4mm, and is capable of operating more than 7 months from two AA batteries

Short wavelength infrared (SWIR) photovoltaic diode structures made of InGaAs material were grown on GaAs by means of molecular beam epitaxy. Growth quality and composition of the layers are determined by HRXRD. The electrical characterization is performed by Current-Bias characterization (proposal) and spectral resolved measurements to determine the resistance area product (R0A) and the spectral responsivity (R) of diodes. The processing is performed with standard photolithography and micro-structuring techniques aiming at the production of 1D and 2D infrared camera arrays. The diced IR sensor is flip chip assembled on a Silicon read out integrated circuit (ROIC). Linear arrays of 256 pixels with 25 μm pitch were fabricated as well as focal plane arrays (FPA) of 256 × 320 pixel with 30 μm pitch. Measures of electrical interconnection yield will be shown. Functionality is proven for different applications up to 2.5 μm wavelength.

The photoconductor detector arrays for the PACS instrument (Photoconductor Array Camera and Spectrometer) aboard the future ESA telescope Herschel have been developed during the engineering phase in 1999. In early 2000 the construction of the qualification models began for both, the highly and low stressed Ge:Ga arrays, which consist of 12 linear modules each. These two types of photoconductor arrays are dedicated for different wavelengths bands in the spectrometer section of the instrument. While the performance of a few engineering arrays has been studied and presented earlier, additional data are meanwhile available on the absolute responsivity and quantum efficiency of the detectors. Furthermore, experience has been obtained during manufacture of a larger series of arrays giving better statistics on performance aspects, such as uniformity of the cutoff wavelengths and of the responsivity or the maximum stress obtainable within such arrays. Considerable progress has also been made in the development and manufacture of the 4 Kelvin Cold Read-out Electronics (CRE), which will integrate and multiplex the signals generated in each linear array with its 16 detector pixels. Manufacture of the detector arrays for the qualification model is scheduled to be completed by this summer, and manufacture of the flight model has already started. The qualification model will be delivered to the test facilities, where absolute spectral performance of the 24 linear modules will be determined. In this paper we give a summary of the related activities and results as obtained during manufacturing and testing.

Short-wave IR and mid-IR photovoltaic detector arrays consisting of In(Ga)As and InAsSb were realized. Maximum array size is 256 X 256 elements on a 25 micron pitch. The layers were grown on 3' semi-insulating GaAs substrates by MBE thereby avoiding the need for substrate removal by wafer thinning after hybridization. A reliable and uniform detector process using improved wet-etching has been developed. The citric-acid based etch has been optimized for minimum underetch such that high fill factor is achieved even with a mesa-type process. Typical R_oA products at room temperature are within a factor of 2 of the theoretical limit for bulk leakage currents. The hybridization with silicon readout circuits consisted of Si-postprocessing by electroless plating or lithographic definition of Ni/Au, indium bump electroplating on the III-V chip and flip-chip integration with individual indium bumps. The indium bump process resulted in 13 micron diameter solderbumps which allows pixel pitches below 20 micron.