Koichi Tanno

In this study, we propose the systematic offset voltage reduction method considering the channel length modulation effect for the two-stage CMOS operational amplifiers (Op-Amps) and comparators. The proposed method employs the half-circuit of the input stage in two-stage Op-Amps as the output stage. Using the proposed method, each terminal voltage of the MOS transistors in the input and output stages is aligned, and the channel length modulation effect can be ignored. To generalize the proposed method, we applied the proposed method to Op-Amps with the cascode active load and differential difference amplifier. The systematic offset voltage was evaluated and compared by simulation using HSPICE with TSMC 0.18 μm model parameters. Consequently, we confirmed that the proposed method can reduce the systematic offset voltage by 95% or more.

In the need for artificial intelligence application on the analog circuit design automation, larger and larger datasets containing analog and digital circuit pieces are required to support the analog circuit recognition systems. Since analog circuits with almost similar designs could produce completely different outputs, in case of poor netlist to graph abstraction, larger netlist input circuits could generate larger graph dataset duplications, leading to poor performance of the circuit recognition. In this study, a technique to detect graph dataset duplication on big data applications is introduced by utilizing the output vector representation (OVR) of the untrained Graph Neural Network (GNN). By calculating the multi-dimensional OVR output data into 2-dimentional (2D) representation, even the random weighted untrained GNN outputs are observed to be capable of distinguishing between each graph data inputs, generating different output for different graph input while providing identical output for the same duplicated graph data, and allowing the dataset’s duplication detection. The 2D representation is also capable of visualizing the overall datasets, giving a simple overview of the relation of the data within the same and different classes. From the simulation result, despite being affected by the floating-point calculation accuracy and consistency deficiency, the F1 score using floating-point identical comparisons are observed with an average of 96.92% and 93.70% when using CPU and GPU calculations, respectively, while the floating-point rounding calculation is applied. The duplication detection using floating point range comparison is the future work, combined with the study of the 2D GNN output behavior under the ongoing training process.

This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.

Emotional conditions cause changes in the speech production system. It produces the differences in the acoustical characteristics compared to neutral conditions. The presence of emotion makes the performance of a speaker verification system degrade. In this paper, we propose a speaker modeling that accommodates the presence of emotions on the speech segments by extracting a speaker representation compactly. The speaker model is estimated by following a similar procedure to the i-vector technique, but it considerate the emotional effect as the channel variability component. We named this method as the emotional variability analysis (EVA). EVA represents the emotion subspace separately to the speaker subspace, like the joint factor analysis (JFA) model. The effectiveness of the proposed system is evaluated by comparing it with the standard i-vector system in the speaker verification task of the Speech Under Simulated and Actual Stress (SUSAS) dataset with three different scoring methods. The evaluation focus in terms of the equal error rate (EER). In addition, we also conducted an ablation study for a more comprehensive analysis of the EVA-based i-vector. Based on experiment results, the proposed system outperformed the standard i-vector system and achieved state-of-the-art results in the verification task for the under-stressed speakers.

Speech activity detection (SAD) or sometimes called voice activity detection (VAD), is a crucial part of most speech-related applications. The SAD system serves to ensure the primary system processes only speech segments. Many speech-based systems have reported that detection accuracy is thanks to the robustness of their SAD system. Various SAD methods have been explored and enhanced in addressing noisy environments, but a few of them notice the emotional condition of the speakers. Whereas, in real conditions, emotions (such as stress) can pose a considerable impact on SAD system performance. In this paper, we propose a compact SAD system that is able to harmonize with the altered speech characteristics due to the presence of emotion and also powerful in high noise conditions. Since there is a similarity between emotional effect and channel effect, the advantages of the proposed SAD system is the applied of a new channel compensation scheme (termed as embedded discriminant analysis, EDA) that works in the i-vector space. We design the EDA in such a way so that it could compensate the presence of emotional condition. EDA transforms original i-vector to a lower-dimensional denoise embedding space. We develop EDA as simple and efficient as the linear discriminant analysis (LDA). The cosine similarity algorithm is applied to calculate the resemblance score between the audio target and the speech/non-speech models, and also for deciding the decision threshold. The effectiveness of the proposed SAD system is evaluated in the clustering task of Speech Under Simulated and Actual Stress (SUSAS) data, that aimed for the stress speech clustering (SSC) system. Contribution-We propose a SAD system which not only strong in noisy environments but also be able to compensate the presence of emotional conditions.

Sleep disorder is a medical disease of the sleep patterns, which commonly suffered by the elderly. Sleep disorders diagnosis and treatment are considered to be challenging due to a time-consuming and inconvenient process for the patient. Moreover, the use of Polysomnography (PSG) in sleep disorder diagnosis is a high-cost process. Therefore, we propose an efficient classification method of sleep disorder by merely using electrocardiography (ECG) signals to simplify the sleep disorders diagnosis process. Different from many current related studies that applied a five-minute epoch to observe the main frequency band of the ECG signal, we perform a pre-processing technique that suitable for the 30-seconds epoch of the ECG signal. By this simplification, the proposed method has a low computational cost so that suitable to be implemented in an embedded hardware device. Structurally, the proposed method consists of five stages: (1) pre-processing, (2) spectral features extraction, (3) sleep stage detection using the Decision-Tree-Based Support Vector Machine (DTB-SVM), (4) assess the sleep quality features, and (5) sleep disorders classification using ensemble of bagged tree classifiers. We evaluate the effectiveness of the proposed method in the task of classifying the sleep disorders into four classes (insomnia, Sleep-Disordered Breathing (SDB), REM Behavior Disorder (RBD), and healthy subjects) from the 51 patients of the Cyclic Alternating Pattern (CAP) sleep data. Based on experimental results, the proposed method presents 84.01% of sensitivity, 94.17% of specificity, 86.27% of overall accuracy, and 0.70 of Cohen’s kappa. This result indicates that the proposed method able to reliably classify the sleep disorders merely using the 30-seconds epoch ECG in order to address the issue of a multichannel signal such as the PSG.

In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < V_DD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and V_DD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when V_DD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications.

Real stressed speech is affected by various aspects (individual characteristics and environment) so that the stress patterns are diverse and different on each individual. To this end, in our previous work, we performed an unsupervised clustering method that able to self-learning manner by mapping the feature representations of the stress speech and clustering tasks simultaneously, called deep time-delay embedded clustering (DTEC). However, DTEC has not confirmed yet the compatibility between the output class and informational classes. Therefore, we proposed semi-supervised time-delay embedded clustering (SDTEC) as a new framework of semi-supervised in DTEC. SDTEC incorporates the prior information of pairwise constraints in the embedding layer and simultaneously learns the feature representation and the clustering assignments. The prior information was used to guide the clustering procedure so that the points that belong to the incorrect cluster can be corrected. The effectiveness of the proposed SDTEC was evaluated by comparing it with some baseline methods in terms of the clustering error rate (CER). Moreover, to demonstrate SDTEC’s capabilities, we conducted a comprehensive ablation study. Based on experiment results, SDTEC outperformed the baseline methods and achieves state-of-the-art results in semi-supervised clustering.