Tomoyuki Shoji

The aims of this paper are to elucidate the short-circuit failure mechanism of SiC MOSFETs that causes mechanical failure of the interlayer dielectric adjacent to the gate, to find the relationship between short-circuit withstand capability and short-circuit failure time, and to classify failure modes by the short-circuit failure time. When the short-circuit failure time is shorter than a certain time, the stresses acting on the interlayer dielectric caused by the thermal expansion of the SiC-die exceed the fracture stress limit of the oxide films. Therefore, cracks occur at the interlayer dielectric, between the gate and the source. In this case, the short-circuit withstand capability can be predicted by thermal theory because the thermal expansion of the SiC-die is determined by the temperature rise. However, when the short-circuit failure time is longer than a certain time, the stresses acting on the interlayer dielectric are less than the fracture stress limit of the oxide films. Thus, the failure mode changes to metallization short mode without causing interlayer dielectric cracks. Thermal stress simulations and experiments ascertain that the stress acting on the interlayer dielectric due to the thermal expansion of SiC varies with the short-circuit failure time, resulting in an altered failure mode.

The triggering mechanism for cosmic ray neutron‐induced single‐event burnout (SEB) in silicon insulated‐gate bipolar transistors (IGBTs) and diodes was investigated by white neutron‐irradiation experiments and transient device simulations. Electron‐hole pairs are generated along the tracks of recoil ions produced by nuclear spallation reactions between incident neutrons and the constituent nuclei of the device. In the vicinity of the n ⁻ /n ⁺ interface, the resulting dynamic current causes an increase in the electron density, and the space charge effect of the carriers leads to an increase in the peak electric field. In an IGBT, the onset of impact ionisation at this interface can cause a parasitic transistor to switch on. In the case of diodes, the electric field distribution leads to diode secondary breakdown. Therefore, impact ionisation at the n ⁻ /n ⁺ interface is essential for triggering SEB. In this study, analytical equations are derived for the local rise in temperature during SEB. The local temperature rise is proportional to the energy, defined in terms of the product of the applied voltage and the total avalanche charge. The diameter of the damage region estimated using these equations is similar to the size of the observed annular voids.

Cosmic ray neutrons can trigger catastrophic failures in power devices. It has been reported that parasitic transistor action causes single-event burnout (SEB) in power metal–oxide–semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). However, power diodes do not have an inherent parasitic transistor. In this paper, we describe the mechanism triggering SEB in power diodes for the first time using transient device simulation. Initially, generated electron–hole pairs created by incident recoil ions generate transient current, which increases the electron density in the vicinity of the n^-/n⁺ boundary. The space charge effect of the carriers leads to an increase in the strength of the electric field at the n^-/n⁺ boundary. Finally, the onset of impact ionization at the n^-/n⁺ boundary can trigger SEB. Furthermore, this failure is closely related to diode secondary breakdown. It was clarified that the impact ionization at the n^-/n⁺ boundary is a key point of the mechanism triggering SEB in power devices.