Narendra Kumar

The rapid growth of wideband wireless communication and edge intelligence applications has driven stringent requirements for analog to digital converters (ADCs) that simultaneously achieve high sampling rates, robust dynamic performance, energy efficiency, and scalability across advanced CMOS technology nodes. This paper presents a comprehensive review of high-speed CMOS ADC architectures, including flash, advanced flash, successive approximation-register (SAR), pipelined, pipelined-SAR, and time-interleaved (TI) designs, with emphasis on their suitability for emerging 5G New Radio (NR) and artificial intelligence (AI)-edge systems. Recent state of art CMOS implementations are critically examined and benchmarked, and the fundamental trade-offs among sampling speed, resolution, power consumption, and silicon area are systematically analyzed across different architectures and technology nodes. Key architectural techniques and scaling trends enabling performance improvement are discussed, together with a comparative evaluation using Schreier Figure of Merit (FoMS). The analysis indicates that continued CMOS scaling and architectural innovation have enabled FoMS values exceeding 160 dB, meeting the demands of low-power, high speed, and high resolution data conversion in next-generation wireless and artificial intelligence (AI)-edge platforms.

With the advancement of agricultural automation and the IoT, drone-based pesticide spraying has become a crucial method for improving operational efficiency and accuracy, particularly for pest control in tall crops such as durian orchards. Traditional manual spraying often struggles with achieving uniform coverage due to the high and dense canopies, leading to pesticide waste and environmental pollution. This study proposes the IoT drone-based pesticide spraying method using the IM-PID control algorithm to address the common issue of uneven spraying in durian orchards. By combining particle swarm optimization (PSO) with the PID control algorithm and IoT sensors, the IM-PID algorithm can adjust spray flow rate and droplet distribution in real time, maintaining high accuracy in complex environments. Experimental results show that the IM-PID algorithm improves spraying uniformity and accuracy across various flight strategies and canopy levels. Compared to other commonly used algorithms like FZ-PID, GC-PID and RL-PID, the IM-PID algorithm offers significant advantages in reducing spraying deviation, improving pesticide utilization and minimizing environmental pollution.

This paper presents a novel design methodology for an outphasing Class-E power amplifier operating at 27.12 MHz, specifically addressing limitations inherent to traditional outphasing combiners that utilize distributed microstrip transmission lines for harmonic termination. At MHz frequencies, conventional microstrip techniques become impractical due to excessively large physical dimensions. To overcome this, the proposed design employs an entirely lumped-element combiner network, eliminating the need for distributed microstrip harmonic terminations. A rigorous analytical framework is derived using two-port impedance matrices, ensuring simultaneous impedance matching at both peak and back-off power conditions. Parametric studies optimize component values, resulting in enhanced efficiency and stable output power across a broad range of outphasing angles. A prototype employing GaN-based transistors demonstrates high efficiency of 73.2% at peak output power and maintains above 50% efficiency at 6 dB output back-off, validating the effectiveness and practicality of the proposed lumped-element approach. This compact and efficient configuration offers significant advantages for MHz-band RF transmitters and wireless power transfer systems.

This paper presents a comprehensive review of engineering techniques employed to enhance the quality factor (Q-factor) of silicon-based on-chip inductors across MHz-to-GHz frequency domains. The performance of CMOS on-chip inductors is often bottlenecked by the substrate losses, parasitic effects and resistive losses, which degrade the Q-factor. Numerous engineering techniques including substrate engineering, ground plane engineering, layout engineering and material engineering are analyzed and discussed. Substrate engineering such as substrate isolation and micromachining, ground plane engineering such as patterned ground shield and defected ground shield, layout engineering such as multilayer stacking and geometry modulation, material engineering such as magnetic core integration and conductor lamination are all investigated. A comparative evaluation of these techniques highlights the optimum approaches for attaining high-Q inductors in silicon process, mainly for CMOS compatibility.

The semiconductor industry plays a vital role in modern technology, with semiconductor devices embedded in almost all electronic products. As these devices become increasingly complex, ensuring quality and reliability poses significant challenges. Electrical testing on semiconductor wafers for defects is crucial, but paradoxically, the testing process itself can introduce defects. These test-induced defects could remain undetected on the wafer, proceed through assembly, and may only be discovered later by customers, leading to returns and significant yield loss. This study proposes a novel graph-based semi-supervised learning (GSSL) algorithm to identify these test-induced hidden defects on the semiconductor wafer that escape conventional methods. The algorithm, which incorporates domain knowledge in creating a graph representation of wafer, and utilizing a weighted edge label propagation model, has demonstrated its effectiveness by achieving a 68% accuracy on a real-world dataset, offering a promising approach to enhance quality control in semiconductor manufacturing.

In this paper, a CMOS Class-J Doherty power amplifier (PA) integrating a Class-G driver and an Impedance-Modulated-Quadrature-Transformer (IMQT) to enhance back-off efficiency for multimode operations is presented. The Class-J Doherty PA utilizes a second harmonic termination to improve its efficiency. To further augment efficiency at deep back-off output power, a single-supply-rail Class-G driver operates with the IMQT, modulating the interstage impedance between the driver and the Doherty stages. The IMQT features a stacked transformer architecture and dynamically adjusts its impedance by switching a floating, intermediate coil between the transformer's primary and secondary windings. A comparator regulates the IMQT based on the Class-G driver's operation. The IMQT-DPA, fabricated using a 65nm CMOS process, operates at a center frequency of 28 GHz with a supply headroom of 1.8V. The PA achieves an average output power of 14 dBm with a back-off efficiency of 21%, representing a 1.4-fold efficiency enhancement compared to conventional Class-B operation. Under low-power mode (V_DD/2) with a Class-G driver operation, the average output power is 11.3 dBm with a 1.3-fold efficiency improvement.

Achieving precise localization in industrial settings presents significant challenges due to dynamic movements, complex layouts, and harsh environmental conditions that cause signal interference and reflections. This requires developing advanced indoor positioning systems that can handle these challenges and perform reliably even in the presence of dynamic movement. In this paper, a novel LoRa-based indoor positioning system designed for dynamic motion in industrial environments is presented. The proposed system integrates LoRa technology with a fingerprinting approach that involves fingerprint collection using the constant motion method and leverages a two-layer Deep Gaussian Process Regression (DGPR) model to overcome the non-linearity characteristics of signal propagation. Through testing on static and motion datasets, it was observed that collecting data in motion yields superior results for tracking dynamic objects. Furthermore, temporal-based enhancements like Temporal Weighted RSSI Averaging and Kalman filtering were introduced. These techniques effectively mitigate RSSI temporal variations and improve the reliability of position estimates. The experimental results, conducted in a real industrial environment, demonstrate that the proposed system achieves a mean positioning error of 1.94 meters and a 90th percentile error of 3.28 meters. These findings highlight the potential of combining LoRa technology with advanced machine learning algorithms and filtering techniques to achieve precise and reliable indoor tracking.

This paper presents a high speed 16-bit hybrid Digital-to-Analog converter (DAC) featuring an innovative digital filtering mechanism designed to eliminate glitches and ensure high signal integrity at an operational speed of 1 GS/s. Fabricated using a 65 nm process and operating on a 1 V supply, the hybrid DAC integrates a current-steering architecture for the six most significant bits (MSB) and a binary-weighted resistive ladder for the ten least significant bits (LSB), effectively managing power consumption. Occupying an active area of 0.06 mm ² , the DAC consumes 45 mW of power. It demonstrates differential nonlinearity (DNL) ranging from -0.27 to +0.25 LSB and integral nonlinearity (INL) from -0.33 to +0.34 LSB. Performance metrics at the Nyquist frequency include a spurious-free dynamic range (SFDR) of 72 dB and a signal-to-noise-and-distortion ratio (SNDR) of 70 dB, yielding a figure of merit (FOM) of 13.83 fJ/step. The DAC demonstrates resilience to process, voltage, and temperature (PVT) variations, with a deviation of less than 4%, confirming its reliability for the 5G New Radio (NR) sub-6 GHz application. The proposed hybrid DAC provides a fast, accurate, and power-efficient solution for high-speed, high-resolution data conversion catering to the demanding requirements of 5G NR sub-6 GHz systems.

The traditional method of detecting crop nutrients is based on the direct chemical detection method in the laboratory, which causes great damage to crops. In order to solve the above problems, the main goal of this study is to design a precise fertilization method for greenhouse vegetables based on the improved back-propagation neural network (IM-BPNN) algorithm to increase fertilizer utilization efficiency, reduce production costs, and improve the economic viability of agriculture. First, soil samples from the farm in china are selected. With the laboratory treatment, available phosphorus, available potassium, and alkaline nitrogen are extracted. These data are preprocessed by the z-score (zero-mean normalization) standardization method. Then, the BPNN (backpropagation neural network) algorithm is improved by being trained and combined with the characteristics of the dual particle swarm optimization algorithm. After that, the soil sample data are divided into training and test sets, and the model is established by setting parameters, weights, and network hierarchy. Finally, the NBTY (nutrient balance target yield),BPNN (backpropagation neural network) and IM-BPNN algorithm are used to calculate the amount of fertilizer. Compared with the BPNN and NBTY algorithm, it shows that the IM-BPNN algorithm can more accurately determine the amount of fertilizer required by vegetables and avoid over-application, which can improve fertilizer utilization efficiency, reduce production costs, and improve the economic feasibility of agriculture.