Karl-Friedrich Becker

This paper focuses on developing a contactless jetting technique to apply a novel microparticle-based silver (Ag) sinter paste suitable for pressureless sintering of miniaturized optoelectronic components. Traditional soldering methods encounter challenges at high temperatures, which can be addressed by employing advanced sintering techniques. In these techniques, the use of adapted materials plays a pivotal role in facilitating process adaptation. We detail the optimization of a contactless jet dispensing process and analyze the influence of key parameters, such as cartridge pressure, needle lift, rising time, and open time, on the precision and reliability of material deposition. We develop a volumetric flow model to characterize the jetting process, which enables fine control over the deposited dot volume and shape. Through experimental validation using square-footprint LED dice, we demonstrate a linear correlation between open time and dot volume while highlighting falling time as a free parameter affecting dot morphology. This methodology demonstrates the potential for the accurate and efficient application of sintering pastes in optoelectronic packaging and paves the way for future advancements in microelectronic assembly.

Fan-out wafer-level packaging (FOWLP) is an interesting platform for Microelectromechanical systems (MEMS) sensor packaging. Employing FOWLP for MEMS sensor packaging has some unique challenges, while some originate merely from the fabrication of redistribution layers (RDL). For instance, it is crucial to protect the delicate structures and fragile membranes during RDL formation. Thus, additive manufacturing (AM) for RDL formation seems to be an auspicious approach, as those challenges are conquered by principle. In this study, by exploiting the benefits of AM, RDLs for fan-out packaging of capacitive micromachined ultrasound transducers (CMUT) were realized via drop-on-demand inkjet printing technology. The long-term reliability of the printed tracks was assessed via temperature cycling tests. The effects of multilayering and implementation of an insulating ramp on the reliability of the conductive tracks were identified. Packaging-induced stresses on CMUT dies were further investigated via laser-Doppler vibrometry (LDV) measurements and the corresponding resonance frequency shift. Conclusively, the bottlenecks of the inkjet-printed RDLs for FOWLP were discussed in detail.

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm² panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

The implementation of additive manufacturing technology (e.g., digital printing) to the electronic packaging segment has recently received increasing attention. In almost all types of Fan-out wafer level packaging (FOWLP), redistribution layers (RDLs) are formed by a combination of photolithography, sputtering and plating process. Alternatively, in this study, inkjet-printed RDLs were introduced for FOWLP. In contrast to a subtractive method (e.g., photolithography), additive manufacturing techniques allow depositing the material only where it is desired. In the current study, RDL structures for different embedded modules were realized by inkjet printing and further characterized by electrical examinations. It was proposed that a digital printing process can be a more efficient and lower-cost solution especially for rapid prototyping of RDLs, since several production steps will be skipped, less material will be wasted and the supply chain will be shortened.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

For radar applications, the W-band frequency range (75 – 110 GHz) is a good candidate for high-resolution distance measurement and remote detection of small or hidden objects in distances of 10 cm to ≫ 20 m. As electromagnetic waves in this frequency range can easily penetrate rough atmosphere like fog, smoke or dust, W-band radars are perfectly suited for automotive, aviation, industrial and security applications. Additional benefit is that atmosphere has an absorption minimum at 94 GHz, so relative small output power is sufficient to achieve long range coverage. By combining and enhancing knowledge from the disciplines of heterogeneous integration technology and compound semiconductor-technology, the Fraunhofer Institutes IAF, IPA and IZM developed a miniaturized and low cost 94 GHz radar module. Result of this approach is a highly miniaturized radar module built using a modular approach. The radar components are mounted on a dedicated RF-NF-hybrid PCB while the signal processing is done on a separate board stacked below. This hybrid RF-module is combined with highly integrated digital processing PCB via micro connectors in a way that the radar system and an adapted conical HDPE-lens fit into an aluminum housing of 42×80×27 mm3 with a weight of only 160 grams for the whole module. The paper will describe the technological basis for such a frequency modulated continuous wave [FMCW] W-band radar module and describe in detail the technological features that enabled the assembly of such a miniaturized but high-performance system. The module yields an evaluated distance measurement accuracy of 5 ppm (5 μm deviation per meter target distance) while its low weight and small dimensions pave the way for a variety of new applications, including mobile operation.

During the last years, jetting processes for higher viscosity materials have gained widespread interest in microelectronics manufacturing. Main reasons for this interest are high throughput/productivity of jetting, contactless material deposition, high volume precision and freely designable deposition patterns. In previous studies [i,ii] we have demonstrated the jetability of different resin-based materials, being exemplary for unfilled adhesive, for low viscous Underfill resin and for higher viscosity Glob Top materials. The focus of our previous work was on the dosing of various encapsulants - Underfill material with low viscosity and near Newtonian behaviour and Glob Top resins, being non-Newtonian fluids due to higher matrix viscosity and higher filler content (up to 70 wt %) with resulting increased filer/filler and filler/matrix interaction. During the last years jetting has become widely used and has been applied to the dosing of much more complex materials, combining high viscosity matrix materials with odd shaped and compressive particles. Examples for these materials are conductive adhesives and also solder pastes, where the jetting system developed by Swedish company Mydata set's the current standard for solder paste jetting. In a technological study solder paste jetting using different jetting systems has been investigated in comparison to solder paste dispensing and solder paste printing, especially material rheological behaviour and the correspondence to processability have been evaluated in detail. To illustrate the potential of solder paste jetting as a flexible and powerful tool for electronic system prototyping, a test vehicle has been designed, containing areas for SMD soldering and for process reproducibility. To determine process quality not only basic process data on droplet diameter, resulting material depot size and positioning accuracy have been evaluated, but also statistical means have been employed to determine process homogeneity and stability depending on the respective parameter set. Summarized this paper gives an insight into solder jet process development and describes material rheology demands and limitations and thus allows the optimized use of advanced solder jetting technology for electronics assemblies.

During the last years within power electronics packaging a trend towards compact power electronics modules for automotive and industrial applications could be observed, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics yielding maximum miniaturization. Transfer molding is the method of choice for cost effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package: Typically those packages are asymmetric, a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed providing a heat path for optimized cooling. This asymmetric geometry is prone to yield warped substrates, preventing optimum thermal contact to the heatsink and also putting thermo-mechanical stress on the encapsulated components, possibly reducing reliability. Such packages being truly heterogeneous, combining powerICs, wire bonds, SMDs, controlICs, substrate and leadframe surfaces, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally those packages need to operate at elevated temperatures for long time, e.g. operate at 200 °C for 1000 h and more, so high thermal stability is of ample importance. Within this paper the main goal is to identify transfer molding compounds suitable for the encapsulation of smart power modules, ready to be used at 200 °C and determine the actual maximum temperature of use of such high performance molding compounds currently available in the market. Summarized a detailed description of the high temperature suitability of high performance molding compounds is provided – additionally an extended test methodology is described to facilitate future material evaluation for HT or harsh environment use of polymeric materials as encapsulants or base materials.

In recent years, within power electronics packaging, there has been a trend toward compact power electronics modules for automotive and industrial applications, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics, yielding maximum miniaturization. Transfer molding is the method of choice for cost-effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package. Typically, these packages are asymmetric, and thus a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed, providing a heat path for optimized cooling. This asymmetric geometry is prone to yielding warped substrates, preventing optimum thermal contact to the heat sink and also putting thermomechanical stress on the encapsulated components, possibly reducing reliability. Such packages are truly heterogeneous, combining power ICs, wire bonds, SMDs, control ICs, substrate, and lead frame surfaces. As a result, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally, those packages need to operate at elevated temperatures for extended time periods, for example, at 150°C for 2000 h and more, so high thermal stability is of prime importance. Within this paper, a reference application is described integrating power and control logic inside a lead frame based molded package. Taking into account the challenges mentioned above, a detailed description of material selection for this module will be given, including material analysis, such as rheology, reactivity, and change in εr; and thermomechanical properties, in initial stage as f(t,T) and after media storage. Process development tools for module molding are used to ensure manufacturability and usability. Concluding rules for encapsulant material selection and package setup are provided.

During the last years, jetting processes for higher viscosity materials have gained widespread interest in microelectronics manufacturing. Main reasons for this interest are high throughput/productivity of jetting, contactless material deposition, high volume precision and freely designable deposition patterns. In previous studies we have demonstrated the jetability of different resin-based materials, being exemplary for unfilled adhesive, for low viscous Underfill resin and for higher viscosity Glob Top materials. The focus of our previous work was on the dosing of Underfill material, where this study is dealing with more complex materials – Glob Top resins. These materials are non-Newtonian fluids - the flow curves of the filled materials can be described by models of Cross or Herschel/Bulkey. Furthermore, highly filled and paste-like mixtures show a significant time dependency of formation of structural equilibrium after deformation, so process development needs to take this into account, so detailed material analysis is described within this study. To illustrate the potential of jetting as a flexible and powerful tool for Chip on Board encapsulation, both, simple test-structures (dots, lines, dams) but also more complex demonstrators have been assembled using wire bonded ICs on ceramic substrates and encapsulants showing viscosities ranging from 10 Pas to > 100 Pas. Not only basic process data on droplet diameter, resulting material depot size and positioning accuracy have been evaluated, but also statistical means have been employed to determine process homogeneity and stability depending on the respective parameter set. Additionally, the whole process was followed by a high-speed camera system, providing detailed information on actual jetting behaviour during droplet release, flight and impact. Summarized this paper gives a detailed insight into jet process development for high viscosity Glob Top materials and describes process design rules and limitations and thus allows the optimized use of advanced jetting technology for Chip on Board assemblies.