Tanvir Hussain

IEC 61499 holds its distinct identity as a standard modeling language for distributed control applications in the realm of Industrial Process Measurement and Control Systems (IPMCSs). From the perspective of modeling distributed control applications it seems to be a fitting standard unless one tries to map the models into implementations on any of the diverse hardware platforms available for IPMCS. UML often seems to be a modeling counterpart of IEC 61499. Due to its wide-spread application in different domains UML is now enriched enough with artifacts like standard profiles and hence more expressive. Moreover, its familiarity inspired researchers to draw modeling similes with IEC 61499. In this context the presented work tries to present the aspects of UML artifacts to specify IEC 61499 models to avoid certain ambiguities that might widen the gap between model and implementation. Moreover, considering the fact that the model of IEC 61499 resources and its mapping to implementation determines how the constituent element should behave in the application, a modeling paradigm for resources - taking into account the execution semantics (profile) - in terms of UML is also proposed. Its uniqueness lies in the fact that the ambiguity of textual representation is sufficiently avoided. Furthermore, the definition in terms of constraints (OCL) allows checking a model for consistency with a given profile.

Development of distributed control applications within a standard framework was actually the strongest motivation behind the introduction of IEC 61499. Yet, scarcity of its application is due to the fact that the development is more complex as compared to the existing languages and standards. This paper addresses an UML-based development process for IEC 61499 which attempts to consider the aspects related to the utilization of the unique features that this standard brought into the field of industrial control applications. Reliability is an important consideration in this particular realm of software development and apart from formal verification tests are often performed to verify the software components. An automatic test-case generation methodology is introduced to complement the proposed development process.