Jing Chen

Hydrophobic surfaces have attracted great attention due to their ability to repel water, and metallic surfaces are particularly significant as they have several benefits, for example they self-clean and do not corrode in marine environments, but also have several applications in the aircraft, building and automobile industries. Tungsten is an ideal material for metallic surfaces due to its remarkable mechanical properties. However, conventional micromachining methods of micro- or nanostructures, including mechanical fabrication and laser and wet etching are incapable of balancing functionality, consistency and cost. Inspired by the etching process of silicon, deep etching of bulk tungsten has been developed to achieve versatile microstructures with the advantages of high efficiency, large scale and low cost. In this article, fabrication methods of tungsten-based hydrophobic surfaces using an ICP deep etching process were proposed. Micro- or hierarchical structure arrays with controllable sidewall profiles were fabricated by optimizing etching parameters, which then exhibited hydrophobicity with contact angles of up to 131.8°.

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

A microembossed copper microchannel heat sink was designed and fabricated for high‐density cooling in electronics. The microchannel width and aspect ratio were investigated to find out the optimised channel size for microembossing. The fabrication method was based on bulk copper forming including tungsten die inductively coupled plasma etching, hot copper microembossing, inlet/outlet ports punching and sealing. The heat dissipation performances were tested by ceramic heater. The maximum temperature decreased to ∼37°C under different heat fluxes, with the maximum temperature decreased by 69.2% at 50 W/cm ² heat flux. The equivalent heat transfer coefficient reached the value of 6492 W/m ² K. High‐power chip was used as heat source too. The maximum heat flux reached 304.8 W/cm ² when the chip can still function properly at 90.5°C. High cooling performance with the micro‐heat sink proves that microembossing by tungsten die is an alternative process for microchannel heat sink fabrication with batch production and low cost. Taking advantages of simple fabrication process and reutilisation of tungsten die, the technology shows promising potentials in high‐density microcooling systems.

The copper micro-embossing process using tungsten die was investigated in this paper, which can be applied for mass production on micro-electro-mechanical system (MEMS) components. Tungsten die fabricated by inductively coupled plasma etching was applied, because of its high mechanical strength and high accuracy. Both cold and hot micro-embossing were performed. Micro damage of both copper and tungsten was observed in cold micro-embossing, as the pressing force reached up to 10 kN. Hot micro-embossing under 473 K with a pressing force of 6 kN showed fewer micro-defects without damage. The microchannels with smaller space ratios and channel widths had better filling performances, due to their capability against friction or upsetting. The patterns were fully transferred from the tungsten die to copper workpiece with a minimum linewidth of 20 µ m and aspect ratio of up to 1.09. The fabrication method shows the potential for copper MEMS component fabrication in mass production at low-cost.

This paper presents the fabrication and characterization of a low parasitic capacitance and low-stress Si interposer for 2.5-D/3-D integration of stress sensitive MEMS devices. The glass reflow process is utilized to isolate Si posts (through silicon interposer) from Si substrate of a low resistivity to form vertical electrical interconnection. A process is developed and a dummy Si interposer is fabricated. Using the fabricated samples, the Si interposer is characterized in terms of resistance, parasitic capacitance, breakdown voltage, and residue stress test. Air-gapped Si interconnection is measured with a resistance of 0.9 ${\Omega }$ , a parasitic capacitance of 85.12 fF and a breakdown voltage of 250 V at least. The residual stress of Si interposer is also investigated through infrared flare technology and shows a result that less than 30 MPa around the Si interconnection at 350 °C.

Compared with polymer-based biochips, such as polydimethylsiloxane (PDMS), glass based chips have drawn much attention due to their high transparency, chemical stability, and good biocompatibility. This paper investigated the glass molding process (GMP) for fabricating microstructures of microfluidic chips. The glass material was D-ZK3. Firstly, a mold with protrusion microstructure was prepared and used to fabricate grooves to evaluate the GMP performance in terms of roughness and height. Next, the molds for fabricating three typical microfluidic chips, for example, diffusion mixer chip, flow focusing chip, and cell counting chip, were prepared and used to mold microfluidic chips. The analysis of mold wear was then conducted by the comparison of mold morphology, before and after the GMP, which indicated that the mold was suitable for GMP. Finally, in order to verify the performance of the molded chips by the GMP, a mixed microfluidic chip was chosen to conduct an actual liquid filling experiment. The study indicated that the fabricating microstructure of glass microfluidic chip could be finished in 12 min with good surface quality, thus, providing a promising method for achieving mass production of glass microfluidic chips in the future.

This paper develops an annular copper TSV (through silicon via) integration process. Additives, including accelerator, suppressor, and leveler, with different concentrations are employed in the methanesulfonic-based electrolyte. Besides, other influence factors, including current density, forced convection and environment temperature, are also taken into consideration for the sake of annular TSV filling. A same number of samples with annular and fully filled copper TSV, in the same structure parameters and technological conditions, are fabricated, respectively. Electroplating experiment, X-ray inspection, electrical testing as well as reliability testing are performed in order to compare the characterization of the two integration processes. All test results support this proposed annular TSV integration approach has great application prospect for passive interposer applications.

An efficient electron field emitter based on a monolayer graphene coated well aligned Mo tip array has been designed, fabricated, and evaluated. The advantages of this hybrid nanostructure film morphology are explored and discussed. Efficient and stable field emissions with low turn-on fields have been observed with the new devices. It is further found that the combination of graphene and Mo tip array leads to significant improvements in efficiency for the nanoscale heterostructure emitters.