Wenhui Zhu

Tactile perception is essential for fine interaction and environment awareness in next-generation humanoid robots. However, most flexible tactile sensors suffer from a fundamental sensitivity–linearity trade-off, and their responses become highly nonlinear under elevated pressures due to deformation saturation. To address this challenge, we present a capacitive flexible tactile sensor incorporating a gradient-engineered ring-shaped electrode architecture that enables quasi-linear evolution of the effective contact area under compression. The hierarchical geometry activates interfacial contact sequentially across multiple height levels, yielding an approximately linear increase in contact area and effectively suppressing nonlinear distortion at high pressures. As a result, the sensor achieves a high linearity (R² = 0.999) and sensitivity (0.133 kPa⁻¹) across a wide pressure range of 0–325 kPa. The device further enables reliable monitoring of diverse physiological signals, including pulse, respiration, and subtle facial muscle activity. In addition, integrating a hemispherical bump allows the sensor to detect shear-induced deformation and provide real-time feedback during robotic grasping. The sensor also exhibits excellent stability and repeatability under long-term cyclic loading. These results demonstrate the strong potential of the proposed architecture for wearable health monitoring, tactile human–robot interaction, and dexterous robotic manipulation.

Ultra-large multi-chip FCBGA packages are increasingly adopted in high-performance computing, yet their assembly is highly susceptible to warpage-induced defects during high-temperature processing. This work experimentally investigates the effects of assembly sequence and process-stage warpage control using a 102 mm × 102 mm four-die FCBGA test vehicle. Two representative assembly routes, flip-chip-first (FCF) and ring-attach-first (RAF), are systematically compared based on full-process warpage measurements. The results reveal distinct warpage evolution paths governed by free versus constrained substrate conditions. In the FCF route, severe solder-on-pad (SOP) region warpage during chip attach and underfill curing enlarges the chip–substrate gap, significantly increasing the risk of solder non-wetting and bridging. A process-level magnetic compensation approach applied during flip-chip bonding effectively suppresses SOP-region warpage, improves bump height uniformity, and enables stable FCF assembly. In contrast, the RAF route suppresses global warpage through early stiffener attachment but remains vulnerable to localized SOP-region deformation and rapid warpage variation at elevated temperatures, leading to bump-related defects at package corners. These results establish a clear process-warpage-risk relationship. Screening-level JEDEC reliability tests show no functional failure or electrical discontinuity, confirming the feasibility and robustness of the proposed assembly strategy.

This study presents a co-design methodology for high-density double-sided system-in-package (DS-SiP) power modules, combining a novel temporary carrier-based reconstitution process with multi-objective optimization to simultaneously address warpage control and thermo-mechanical reliability. The proposed approach decouples double-sided molding into sequential single-side steps, effectively eliminating strip substrate warpage after the first molding cycle and minimizing process-induced stress. A high-fidelity finite element model was developed to simulate thermo-mechanical behavior and identify critical stress locations at die/EMC and die/adhesive interfaces. The package architecture was optimized using Taguchi-Grey relational analysis, revealing molding material selection as the most influential factor. A test vehicle was successfully fabricated, incorporating through-mold vias (TMVs) and 3D component-on-package (CoP) integration. Reliability tests confirmed strong performance under thermal and humidity stresses, with failure analysis validating simulation predictions of interfacial delamination as the dominant failure mechanism. This work provides a scalable and cost-effective framework for developing robust DS-SiP power modules with improved power density and reliability.

This paper presents a high-accuracy underwater ranging method that integrates a composite MEMS vector–scalar hydrophone with a compact PETN-based explosive sound source. The hydrophone combines a MEMS vector channel for precise direction-of-arrival estimation with a piezoelectric ceramic tube scalar channel for high-fidelity pressure capture, enabling simultaneous acquisition of velocity and pressure signals. The explosive source produces broadband, high-energy pulses that overcome the limited output, narrow bandwidth, and short range of conventional transmitters. Their integration enables accurate echo-based ranging with a single co-located node. A cascaded signal-enhancement process—zero-phase band-pass filtering and improved over-subtraction—suppresses bubble pulses, multipath, and noise in complex environments. Reservoir experiments using a 1 g PETN charge achieved <0.5‰ maximum ranging error and an SNR improvement of 10.8 dB, validating the system’s accuracy, robustness, and suitability for long-range underwater localization.

The increased demand for computing power in artificial intelligence (AI) and high-performance computing (HPC) has led to significant advances in multi-chip integration and large-scale packaging methodologies. This has led to the emergence of multi-chip module (MCM) packaging as a prominent technological approach. However, the coefficient of thermal expansion (CTE) mismatch between the silicon die and organic substrate leads to increased warpage, which in turn causes process and reliability issues such as bump bridging, non-wetting, and solder ball cracking. As a result, warpage control has become a key issue for such products. This study proposes a warpage control method combining material-structure co-design and hybrid intelligent optimization. A 4-die 102 mm × 102 mm flip-chip ball grid array (FCBGA) package simulation model, validated by shadow moiré experiments, achieves ≤ 7.4% prediction error. Warpage exhibits a non-uniform wavy pattern influenced by die layout, with key factors including die space, substrate CTE, stiffener ring CTE, ring foot width and thickness. A custom response surface methodology (RSM) accurately models nonlinear coupling effects, while a hybrid NSGA-II and PSO algorithm optimizes warpage. Full-parameter optimization reduces warpage at 30 °C by 33.5% (138.5 μm) and at 245 °C by 88.3% (28.6 μm), while only stiffener ring optimization delivers even greater improvement at 30 °C with a 50.9% reduction (102.2 μm) along with a 32.2% decrease (166.4 μm) at 245 °C. The proposed approach offers a novel insight and an effective strategy for large-scale MCM package warpage control.

As the demand for efficient heat dissipation in information devices continues to escalate, the heat flux of integrated packaging devices is poised to reach 100 W/cm² universally, rendering microchannel liquid cooling technology a pivotal solution in thermal management. In this work, the microchannel heat sink with spoiler cavities, optimized via field synergy principle, was integrated into the high-power electronics, and its flow and heat transfer performance were experimentally investigated using Al₂O₃-water nanofluid. The results show that the experimental and simulation results of the optimized microchannel heat sink integrated with IGBT devices are in good agreement. With structural optimization combined with an appropriate volume fraction of nanofluid, the microchannel heat sink exhibited significantly better heat dissipation performance than that of rectangular heat sinks under a heat flux of 100 W/cm². Furthermore, when the volumetric flow rate exceeded 0.6 mL/s, the heat transfer performance was improved by 38% compared to the rectangular microchannel heat sink with 1% volume fraction of Al₂O₃-water nanofluid.

As the demand for thermal management of large-size chips grows, indium is considered an ideal thermal interface material (TIM) due to its inherent high thermal conductivity and good ductility. For large-size flip chip packaging, how to enhance reliability, especially under temperature cycling, remains a challenge. With large-size flip chip packaging as its research object this study employed a method that combines finite element simulation and experiments to systematically analyze the creep behavior and morphological evolution of indium under temperature cycling. Based on this analysis, the fatigue life of indium was predicted using the strain-based Coffin-Manson model. To enhance the reliability of the indium layer under temperature cycling, a Design of Experiments (DOE) simulation scheme was used to analyze the influence of varying structural parameters on fatigue life. The results demonstrate that the accumulated plastic strain at the position close to the edge of the chip is the largest, aligning with the position of the crack observed in actual measurements. The fatigue life of the indium layer, as predicted by the Coffin-Manson model, is found to be basically consistent with the measured results. A signal-to-noise ratio (SNR) analysis indicates that the indium thickness has the greatest impact on the thermal fatigue life, while the adhesive thickness has the least impact on the thermal fatigue life. Compared with the original model, the fatigue life of the optimized packaging structure is increased by 135%.

Flip chips have been widely used in microelectronic packaging to meet the requirements of high density and optimal performance; the thermal interface material (TIM) is the primary bottleneck for heat dissipation in flip-chip packages. Vertically aligned thermal pads offer higher thermal conductivity compared with thermal gels, yet their poor interface bonding strength makes their application challenging. In this study, a silane coupling agent (KH550) was applied to improve the bonding strength between the TIM and heat spreader (HS). The presence of the silane coupling agent intermediate layer enabled the TIM and HS to be connected via covalent bonds, greatly improving their bonding strength. The shear strength of the interface between the TIM and HS was increased by 610.7%, and the interface thermal resistance was decreased by 52.78%. Moreover, molecular dynamics simulation was conducted to investigate the interface bonding mechanism.

Traditional packaging with bonded aluminum (Al) wires results to high parasitic inductance and reliability issues, therefore limiting the development of silicon carbide (SiC) power devices. Copper clip (Cu-clip) interconnection process have been proposed, which allows for better heat dissipation and thus enhances the power density of the device. While current research has primarily focused on its thermal performance and reliability, many issues remain unresolved. However, concentrated stress and electrical issue for multi-chip Cu-clip interconnects are still big challenges in the clip-bonded SiC MOSFET power device. Our work proposes an arch clip with unloading groove (Arch-G) structure that can effectively reduce the stress of Cu-clip devices, demonstrating a 39.1% reduction compared with conventional planar clip devices. Compared with wire-bonded devices, the Arch-G clip device boasts lower conduction losses and its parasitic inductance is reduced by 32.6%. Reliability via power cycling test of the Arch-G clip devices were also characterized experimentally. This work serves as a valuable reference for the design of high-performance Cu-clip power device.