Nehru Kandasamy
Research Subjects
Research Interests
Nehru Kandasamy has a total of 35 co-authors. Here are the top co-authors by number of shared publications:
- Nagarjuna Telagam
GITAM University
19 shared publications - Menakadevi Nanjundan
Hindustan College of Engineering and Technology
4 shared publications A. Shanmugam
2 shared publications- Balwinder Raj
Department of ECE, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, India
2 shared publications - D. Ajitha
Sreenidhi Institute of Science and Technology
2 shared publications Arulanandth Ts
1 shared publication
Latest Publications
- 10 December 2025
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 126 (1) , 21
Energy and area efficient 4:2 compressor for sub-10 nm CMOS with gate work function engineered FinFETs
- 10 December 2025
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 126 (1) , 21
Energy and area efficient 4:2 compressor for sub-10 nm CMOS with gate work function engineered FinFETs
- Open Access
- 26 July 2025
- Published by Wiley in IEEJ Transactions on Electrical and Electronic Engineering
- Vol. 21 (2) , 226-234
A Novel Area Efficient and High‐Speed BCD Adder Using CFA and Multiplexer in Quantum‐Dot Cellular Automata
This paper proposes a new enhanced Single Digit BCD Adder (SDBA) to perform decimal addition optimally. Quantum‐dot Cellular Automata (QCA) will construct nanostructured arithmetic circuits for future computing. One of the vital structures in arithmetic structures is the Binary Coded Decimal (BCD)/Decimal Adder. The existing Decimal Adders require many cells and consume more delay, which makes the circuit inefficient in doing decimal addition faster. The binary adder structures are more significant in deciding the performance of conventional BCD adders. Multiplexers are used in the proposed BCD adder to enhance the speed with less complexity. The main contribution of the proposed SDBA design is to replace the final part of the conventional structure Carry Flow Adder (CFA) based BCD adder with a multiplexer, which improves the speed and increases the regularity of the structure. The multiplexers perform the binary to decimal sum conversion in parallel rather than the carry rippling in the lower part of the standard circuit. The SDBA uses the optimized CFA Type‐II binary adder and new logic with a 2:1 multiplexer. Furthermore, the proposed BCD adder is an optimized design in terms of delay, which requires 2.75 clock cycles only compared to the recent designs. © 2025 The Author(s). IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.
- 26 July 2025
- Published by Wiley in IEEJ Transactions on Electrical and Electronic Engineering
- Vol. 21 (2) , 226-234
Open AccessA Novel Area Efficient and High‐Speed BCD Adder Using CFA and Multiplexer in Quantum‐Dot Cellular Automata
This paper proposes a new enhanced Single Digit BCD Adder (SDBA) to perform decimal addition optimally. Quantum‐dot Cellular Automata (QCA) will construct nanostructured arithmetic circuits for future computing. One of the vital structures in arithmetic structures is the Binary Coded Decimal (BCD)/Decimal Adder. The existing Decimal Adders require many cells and consume more delay, which makes the circuit inefficient in doing decimal addition faster. The binary adder structures are more significant in deciding the performance of conventional BCD adders. Multiplexers are used in the proposed BCD adder to enhance the speed with less complexity. The main contribution of the proposed SDBA design is to replace the final part of the conventional structure Carry Flow Adder (CFA) based BCD adder with a multiplexer, which improves the speed and increases the regularity of the structure. The multiplexers perform the binary to decimal sum conversion in parallel rather than the carry rippling in the lower part of the standard circuit. The SDBA uses the optimized CFA Type‐II binary adder and new logic with a 2:1 multiplexer. Furthermore, the proposed BCD adder is an optimized design in terms of delay, which requires 2.75 clock cycles only compared to the recent designs. © 2025 The Author(s). IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.
- Open Access
- 9 May 2025
- Published by International Association of Online Engineering (IAOE) in International Journal of Interactive Mobile Technologies (iJIM)
- Vol. 19 (09) , 19-30
Implementation of IEEE 802.11p for Vehicular Communication: Utilizing NI USRP N321 to Advance Mobile Interactive Technologies
This paper aims to comprehensively implement the Institute of Electrical and Electronics Engineers (IEEE) 802.11p transceiver using the Universal Software Radio Peripheral (USRP) device N321 series for teaching undergraduates. It is a standard in the 802.11 family designed explicitly for wireless access in vehicular environments (WAVE). This process involves configuring the USRP N321 device with IEEE standards, such as adjusting the frequency, amplitude, transmitter gain, direction of the radiation pattern, receiver gain, etc. This transceiver uses an orthogonal frequency division multiplexing (OFDM) modulation scheme. This IEEE 802.11p transceiver provides a practical approach for students and researchers in the realworld platform to analyze wireless communication technologies such as OFDM transceiver, peak-to-average power ratio (PAPR) values, and constellation diagrams for various modulation schemes such as binary phase shift keying (BPSK), quadrature amplitude modulation (QAM), and quadrature phase shift keying (QPSK) with different code rates. The bit error rate values were calculated for the modulation coding schemes index, and data rates of 24 Mbps were achieved for this transceiver.
- 9 May 2025
- Published by International Association of Online Engineering (IAOE) in International Journal of Interactive Mobile Technologies (iJIM)
- Vol. 19 (09) , 19-30
Open AccessImplementation of IEEE 802.11p for Vehicular Communication: Utilizing NI USRP N321 to Advance Mobile Interactive Technologies
This paper aims to comprehensively implement the Institute of Electrical and Electronics Engineers (IEEE) 802.11p transceiver using the Universal Software Radio Peripheral (USRP) device N321 series for teaching undergraduates. It is a standard in the 802.11 family designed explicitly for wireless access in vehicular environments (WAVE). This process involves configuring the USRP N321 device with IEEE standards, such as adjusting the frequency, amplitude, transmitter gain, direction of the radiation pattern, receiver gain, etc. This transceiver uses an orthogonal frequency division multiplexing (OFDM) modulation scheme. This IEEE 802.11p transceiver provides a practical approach for students and researchers in the realworld platform to analyze wireless communication technologies such as OFDM transceiver, peak-to-average power ratio (PAPR) values, and constellation diagrams for various modulation schemes such as binary phase shift keying (BPSK), quadrature amplitude modulation (QAM), and quadrature phase shift keying (QPSK) with different code rates. The bit error rate values were calculated for the modulation coding schemes index, and data rates of 24 Mbps were achieved for this transceiver.
- Open Access
- 25 January 2023
- Published by International Association of Online Engineering (IAOE) in International Journal of Interactive Mobile Technologies (iJIM)
- Vol. 17 (02) , 166-177
Smart Device for Women's Safety Designed Using IoT and Virtual Instrumentation Browser
In the present technological developments, the internet of things (IoT) technology connects all interconnected networks. The attacks on women are increasing daily in Indian countries. If the woman is not carrying a mobile phone or device, she cannot contact the police station or other family members. This proposed method will help the women identify the exact location and inform the police station in such a scenario. The Emergencies, the women, can press the button once the location information is tracked. The purpose of this project is to help women in emergencies. Location tracking and short service messages are also sent to the family members and nearby police stations.
- 25 January 2023
- Published by International Association of Online Engineering (IAOE) in International Journal of Interactive Mobile Technologies (iJIM)
- Vol. 17 (02) , 166-177
Open AccessSmart Device for Women's Safety Designed Using IoT and Virtual Instrumentation Browser
In the present technological developments, the internet of things (IoT) technology connects all interconnected networks. The attacks on women are increasing daily in Indian countries. If the woman is not carrying a mobile phone or device, she cannot contact the police station or other family members. This proposed method will help the women identify the exact location and inform the police station in such a scenario. The Emergencies, the women, can press the button once the location information is tracked. The purpose of this project is to help women in emergencies. Location tracking and short service messages are also sent to the family members and nearby police stations.
- 11 December 2022
- Published by Springer Nature in Journal of Ambient Intelligence and Humanized Computing
- Vol. 14 (3) , 2467-2479
Design of novel low power architectures of 4:2, 5:2 compressors and 2-bit counter using 7 nm FinFET technology
- 11 December 2022
- Published by Springer Nature in Journal of Ambient Intelligence and Humanized Computing
- Vol. 14 (3) , 2467-2479
Design of novel low power architectures of 4:2, 5:2 compressors and 2-bit counter using 7 nm FinFET technology
- 11 June 2022
- Published by Springer Nature in The Journal of Supercomputing
- Vol. 78 (17) , 18666-18690
Novel optimized ultra-dense 1-bit magnitude comparator design in quantum-dot cellular automata technology based on MV32 gate
- 11 June 2022
- Published by Springer Nature in The Journal of Supercomputing
- Vol. 78 (17) , 18666-18690
Novel optimized ultra-dense 1-bit magnitude comparator design in quantum-dot cellular automata technology based on MV32 gate
- 23 August 2021
- Published by Springer Nature in Wireless Personal Communications
- Vol. 121 (4) , 3085-3123
Performance Analysis of Parallel Concatenation of LDPC Coded SISO-GFDM System for Distinctive Pulse Shaping Filters using USRP 2901 Device and its Application to WiMAX
- 23 August 2021
- Published by Springer Nature in Wireless Personal Communications
- Vol. 121 (4) , 3085-3123
Performance Analysis of Parallel Concatenation of LDPC Coded SISO-GFDM System for Distinctive Pulse Shaping Filters using USRP 2901 Device and its Application to WiMAX
- 27 February 2021
- Published by Springer Nature
- p. 637-647
Hybrid 4:16 Decoder Using Variable Bias GDI Technique
- 27 February 2021
- Published by Springer Nature
- p. 637-647
Hybrid 4:16 Decoder Using Variable Bias GDI Technique
- 15 October 2020
- Published by Taylor & Francis in IETE Journal of Research
- Vol. 69 (1) , 535-548
Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register
In the emerging nanotechnology, a finest potential alternative to transistor-based technology is Quantum-dot cellular automata (QCA). It promises higher device density and lower power consumption. The predominant application of QCA is the realization of configurable blocks in the digital systems. This paper presents a new serial scan register and a boundary scan cell, essential components used for chip-level and system-level testing. The proposed majority logic gate-based 1-bit clocked D-flip-flop (DFF) and the rotating multiplexer is used in these techniques. In the first attempt, the clocked DFF is further extended to implement the 2-bit, 4-bit, serial shift register and scan flip-flop. The detailed structural and performance analysis in different aspects proves that the proposed circuits offer elevated performance in contrast to earlier reported works. The various circuit comparison factors that are to be considered in QCA are the circuit complexity, area, delay in terms of the number of clocks, and energy dissipation. Significant improvements have been enhanced in the proposed layouts as compared to traditional approaches. In addition, power dissipation analysis of the stated DFF would be carried out at 2 K Temperature using different tunnelling energy levels (0.5, 1.0, and 1.5 Ek). All the simulations are performed using QCA Designer Ver. 2.0.3 and the power analysis is performed by QCA Pro tool Ver. 1.0.
- 15 October 2020
- Published by Taylor & Francis in IETE Journal of Research
- Vol. 69 (1) , 535-548
Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register
In the emerging nanotechnology, a finest potential alternative to transistor-based technology is Quantum-dot cellular automata (QCA). It promises higher device density and lower power consumption. The predominant application of QCA is the realization of configurable blocks in the digital systems. This paper presents a new serial scan register and a boundary scan cell, essential components used for chip-level and system-level testing. The proposed majority logic gate-based 1-bit clocked D-flip-flop (DFF) and the rotating multiplexer is used in these techniques. In the first attempt, the clocked DFF is further extended to implement the 2-bit, 4-bit, serial shift register and scan flip-flop. The detailed structural and performance analysis in different aspects proves that the proposed circuits offer elevated performance in contrast to earlier reported works. The various circuit comparison factors that are to be considered in QCA are the circuit complexity, area, delay in terms of the number of clocks, and energy dissipation. Significant improvements have been enhanced in the proposed layouts as compared to traditional approaches. In addition, power dissipation analysis of the stated DFF would be carried out at 2 K Temperature using different tunnelling energy levels (0.5, 1.0, and 1.5 Ek). All the simulations are performed using QCA Designer Ver. 2.0.3 and the power analysis is performed by QCA Pro tool Ver. 1.0.
- Open Access
- 30 September 2019
- Published by International Association of Online Engineering (IAOE) in International Journal of Online and Biomedical Engineering (iJOE)
- Vol. 15 (13) , 77-85
USRP Based Digital Audio Broadcasting Using OFDM in Virtual and Remote Laboratory
Digital Audio Broadcasting (DAB) is an amazing technology, achieving its promise of certainly delivering high quality digital audio in the most vindicate mobile and fixed receiver environments. The radio signal processing capability can be provided by Universal software radio peripheral (USRP) hardware. The received signal frequency can be controlled and transmitting the signal through wireless is possible by installing NI USRP utility configuration. The programmable USRP was running the VI snippet program in block diagram panel with radio companion integrated through USB cable on windows 7 64. With the parameters such as IQ rate, transmitter gain, carrier frequency along with device name which is given as ni2901_1 the students can able to tune the radio signal. DAB technology is integrated with USRP device using prominent OFDM technique for promise delivery of high quality audio signal. DAB works under four transmission modes in this paper. In this paper RF0 module is used USRP device is connected with dual band vertical antenna with 2.4 and 5GHz frequency as Tx1. This transmitting VI snippet program will support all file formats such as.wav, mp3, etc. the intention of the paper is to transmit the real time data through long distance using DAB technology in remote laboratory. The proposed system is implemented in virtual lab so that it can be accessed by any user from anywhere. This system is successfully tested on institute of aeronautical engineering virtual lab.
- 30 September 2019
- Published by International Association of Online Engineering (IAOE) in International Journal of Online and Biomedical Engineering (iJOE)
- Vol. 15 (13) , 77-85
Open AccessUSRP Based Digital Audio Broadcasting Using OFDM in Virtual and Remote Laboratory
Digital Audio Broadcasting (DAB) is an amazing technology, achieving its promise of certainly delivering high quality digital audio in the most vindicate mobile and fixed receiver environments. The radio signal processing capability can be provided by Universal software radio peripheral (USRP) hardware. The received signal frequency can be controlled and transmitting the signal through wireless is possible by installing NI USRP utility configuration. The programmable USRP was running the VI snippet program in block diagram panel with radio companion integrated through USB cable on windows 7 64. With the parameters such as IQ rate, transmitter gain, carrier frequency along with device name which is given as ni2901_1 the students can able to tune the radio signal. DAB technology is integrated with USRP device using prominent OFDM technique for promise delivery of high quality audio signal. DAB works under four transmission modes in this paper. In this paper RF0 module is used USRP device is connected with dual band vertical antenna with 2.4 and 5GHz frequency as Tx1. This transmitting VI snippet program will support all file formats such as.wav, mp3, etc. the intention of the paper is to transmit the real time data through long distance using DAB technology in remote laboratory. The proposed system is implemented in virtual lab so that it can be accessed by any user from anywhere. This system is successfully tested on institute of aeronautical engineering virtual lab.