Arun Paidimarri
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Arun Paidimarri has a total of 61 co-authors. Here are the top co-authors by number of shared publications:
- Alberto Valdes-Garcia
IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
5 shared publications - Bodhisatwa Sadhu
IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
4 shared publications - Caglar Ozdag
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
3 shared publications - Yujiro Tojo
Electronic Technologies Research and Development Center, Fujikura Ltd., Chiba, Japan
3 shared publications - Alexandra Gallyas-Sanhueza
IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
2 shared publications Anantha P. Chandrakasan
Massachusetts Institute of Technology, Cambridge, MA, USA
2 shared publications
Latest Publications
- Open Access
- 26 October 2026
- Published by Association for Computing Machinery (ACM)
- p. 1828-1830
Demo: Beam-O-RAN: A Closed-Loop 5G O-RAN Testbed for mmWave Beam Management
- 26 October 2026
- Published by Association for Computing Machinery (ACM)
- p. 1828-1830
Open AccessDemo: Beam-O-RAN: A Closed-Loop 5G O-RAN Testbed for mmWave Beam Management
- 20 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Magazine
- Vol. 17 (4) , 62-78
Toward Spectrally Efficient and Physically Reconfigurable Architectures for Multibeam-Waveform Co-Design in Joint Communication and Sensing: Circuit and system tradeoffs for time-, frequency-, code-, and direct-RF array processing in JCAS/ISAC
Joint Communication and Sensing (JCAS) platforms are emerging as a foundation of next-generation mmWave (MMW) and sub-THz systems, enabling both high-throughput data transfer and angular localization within a shared signal path. This paper investigates multibeam architectures for JCAS that simultaneously optimize waveform shaping and beamforming across the time, frequency, code, and direct analog/ radio frequency (RF) domains. The paper compares Orthogonal Frequency-Division Multiplexing (OFDM), Frequency Modulated Arrays (FMA), Time-Modulated Arrays (TMA), direct RF/MMW modulation, and Code-Division Multiple Access (CDMA)-based systems with respect to spectral efficiency, beam orthogonality, latency, and Angle-of-Arrival (AoA) estimation accuracy. The results highlight architecture-specific trade-offs among beam agility, efficiency, accuracy and resolution, and complexity. It also provides a framework for selecting JCAS front ends optimized for power, latency, inter-beam and multi-user interference, and rapid system reconfiguration.
- 20 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Magazine
- Vol. 17 (4) , 62-78
Toward Spectrally Efficient and Physically Reconfigurable Architectures for Multibeam-Waveform Co-Design in Joint Communication and Sensing: Circuit and system tradeoffs for time-, frequency-, code-, and direct-RF array processing in JCAS/ISAC
Joint Communication and Sensing (JCAS) platforms are emerging as a foundation of next-generation mmWave (MMW) and sub-THz systems, enabling both high-throughput data transfer and angular localization within a shared signal path. This paper investigates multibeam architectures for JCAS that simultaneously optimize waveform shaping and beamforming across the time, frequency, code, and direct analog/ radio frequency (RF) domains. The paper compares Orthogonal Frequency-Division Multiplexing (OFDM), Frequency Modulated Arrays (FMA), Time-Modulated Arrays (TMA), direct RF/MMW modulation, and Code-Division Multiple Access (CDMA)-based systems with respect to spectral efficiency, beam orthogonality, latency, and Angle-of-Arrival (AoA) estimation accuracy. The results highlight architecture-specific trade-offs among beam agility, efficiency, accuracy and resolution, and complexity. It also provides a framework for selecting JCAS front ends optimized for power, latency, inter-beam and multi-user interference, and rapid system reconfiguration.
- 4 February 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 73 (4) , 2073-2083
LO Generation for a 5G Phased Array Transceiver: A High HRR 21–27-GHz Frequency Quadrupler
A 21–27-GHz frequency quadrupler in the 0.13-μm SiGe BiCMOS technology with the 0-dBm output power (POUT) and 40-dBc harmonic rejection ratio (HRR) is presented. A method for load—pull-based output network design is introduced to co-optimize HRR and POUT; as a result, the design achieves flat and high HRR and POUT across 25% bandwidth and a wide input power (PIN) range. This article also discusses the quadrupler’s POUT and HRR specifications in the context of its integration within a phased-array antenna module (PAAM). We designed two versions of the 64-element wideband 5G phased-array PAAM, one including and one excluding the quadrupler, to demonstrate the minimal impact of the quadrupler on the output spectrum. We also measure the spur performance in dual-polarization mode to evaluate cross-polarization spurs. The spurious emissions across POUT range of the phased array is better than -20 dBm/MHz, well below the 3GPP 5G FR2 limit of -15 dBm/MHz. The quadrupler design has the highest HRR performance reported among wideband mmWave quadruplers and thoroughly demonstrates, for the first time, the impact of the local oscillator (LO) frequency multiplier on the performance of a wideband phased-array system.
- 4 February 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 73 (4) , 2073-2083
LO Generation for a 5G Phased Array Transceiver: A High HRR 21–27-GHz Frequency Quadrupler
A 21–27-GHz frequency quadrupler in the 0.13-μm SiGe BiCMOS technology with the 0-dBm output power (POUT) and 40-dBc harmonic rejection ratio (HRR) is presented. A method for load—pull-based output network design is introduced to co-optimize HRR and POUT; as a result, the design achieves flat and high HRR and POUT across 25% bandwidth and a wide input power (PIN) range. This article also discusses the quadrupler’s POUT and HRR specifications in the context of its integration within a phased-array antenna module (PAAM). We designed two versions of the 64-element wideband 5G phased-array PAAM, one including and one excluding the quadrupler, to demonstrate the minimal impact of the quadrupler on the output spectrum. We also measure the spur performance in dual-polarization mode to evaluate cross-polarization spurs. The spurious emissions across POUT range of the phased array is better than -20 dBm/MHz, well below the 3GPP 5G FR2 limit of -15 dBm/MHz. The quadrupler design has the highest HRR performance reported among wideband mmWave quadruplers and thoroughly demonstrates, for the first time, the impact of the local oscillator (LO) frequency multiplier on the performance of a wideband phased-array system.
- Open Access
- 18 December 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Microwaves
- Vol. 5 (1) , 68-83
A Heterogeneously Integrated 256-Element 5G Phased Array: Design, Assembly, Test
In this paper, we present the design, assembly, and test of a heterogeneously integrated dual-polarized 256-element 5G phased array covering 24 $-$ 30 GHz. The design is based on a 64-element antenna-in-package tile designed using an organic substrate. This work represents one of the earliest examples of a heterogeneously integrated mmWave phased array module where each tile uses chips in three different substrate technologies to perform beamforming, frequency conversion, filtering, combining/splitting, and supply decoupling functions. The paper discusses the several challenges and system trade-offs for 5G mmWave phased arrays and illustrates the advantages of heterogeneous integration at the antenna-in-package level. The paper also covers, in detail, several practical aspects of phased array module design that are not well-described in existing literature, such as power domain modeling, module assembly, antenna feedline design, polarization isolation, and tile spacing. To demonstrate the efficacy of our design choices and techniques, we present exhaustive $\pm 360^\circ$ over-the-air beam characterization of the phased array antenna module demonstrating beam scanning over $\pm 70^\circ$ and very low cross-polarization leakage in E-/H-planes in both polarizations and in both TX and RX modes.
- 18 December 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Microwaves
- Vol. 5 (1) , 68-83
Open AccessA Heterogeneously Integrated 256-Element 5G Phased Array: Design, Assembly, Test
In this paper, we present the design, assembly, and test of a heterogeneously integrated dual-polarized 256-element 5G phased array covering 24 $-$ 30 GHz. The design is based on a 64-element antenna-in-package tile designed using an organic substrate. This work represents one of the earliest examples of a heterogeneously integrated mmWave phased array module where each tile uses chips in three different substrate technologies to perform beamforming, frequency conversion, filtering, combining/splitting, and supply decoupling functions. The paper discusses the several challenges and system trade-offs for 5G mmWave phased arrays and illustrates the advantages of heterogeneous integration at the antenna-in-package level. The paper also covers, in detail, several practical aspects of phased array module design that are not well-described in existing literature, such as power domain modeling, module assembly, antenna feedline design, polarization isolation, and tile spacing. To demonstrate the efficacy of our design choices and techniques, we present exhaustive $\pm 360^\circ$ over-the-air beam characterization of the phased array antenna module demonstrating beam scanning over $\pm 70^\circ$ and very low cross-polarization leakage in E-/H-planes in both polarizations and in both TX and RX modes.
- Open Access
- 28 October 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of the Solid-State Circuits Society
- Vol. 4, 193-211
The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation
The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this paper, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meeting these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the up-mixer. We introduce two actuator circuits to control two independent LO signals at the up-mixer output, one resulting from the up-conversion from DC to LO, and another resulting from down-conversion from 2LO to LO. These two independent LO outputs then provide 2-dimensional phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the up-mixer. The LO cancellation results in better than..57 dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a ±60∘ beam steering range.
- 28 October 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of the Solid-State Circuits Society
- Vol. 4, 193-211
Open AccessThe Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation
The wireless spectrum is a shared resource. Transmitters are expected to transmit only at their allotted frequency range and not at other frequencies. Transmitters are not perfect, and therefore, there are regulations that limit the transmitted energy outside the intended transmission frequencies. In this paper, we provide an overview of the transmit mask requirements for 5G FR2, and the main factors that contribute to unwanted emissions. We then present some key radio architecture and circuit design considerations to help meeting these emission requirements. Since the local oscillator (LO) leakage spur is one of the worst offenders, we also introduce an LO cancellation technique in the up-mixer. We introduce two actuator circuits to control two independent LO signals at the up-mixer output, one resulting from the up-conversion from DC to LO, and another resulting from down-conversion from 2LO to LO. These two independent LO outputs then provide 2-dimensional phase and amplitude control and can combine to create an equal and opposite LO signal at the output of the up-mixer. The LO cancellation results in better than..57 dBc LO leakage across all candidate frequencies. Finally, we present extensive over-the-air (OTA) measurement validation of the LO suppression across frequencies, signal levels, and 64-element beam steering across a ±60∘ beam steering range.
- 13 June 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal on Selected Areas in Communications
- Vol. 42 (9) , 2354-2368
Eye-Beam: A mmWave 5G-Compliant Platform for Integrated Communications and Sensing Enabling AI-Based Object Recognition
We present Eye-Beam, a programmable platform for integrated communication and sensing. Eye-Beam leverages the hardware and processing required for standard millimeter-wave (mmWave) 5G directional communications to enable sensing functions. Specifically, our platform (1) receives and synchronizes to the data frame of broadcast 5G signals, (2) extracts directional communication features, creating a tensor of spatial information, and (3) utilizes this data as input to a DNN that infers the presence of specific objects in the propagation environment. Eye-Beam includes a programmable 28 GHz 64-element phased array, an SDR, and custom FPGA-based firmware. Eye-Beam’s key capabilities and metrics include (i) synchronization of I/Q data (up to 200 MSPS) with beam steering (among 9,601 beams) with 10 ns accuracy; (ii) a signal processing pipeline that extracts communication features such as the SNR and channel response from received 5G waveforms; and (iii) system orchestration that synchronizes the receiver (RX) to the 5G frame structure of the base station (gNodeB) and maintains it within a worst-case OFDM cyclic prefix of $0.29~\mu $ s. Eye-Beam is also able to emulate gNodeB transmissions. We demonstrate Eye-Beam’s performance by showcasing its communication capability (decoding up to 64-QAM), as well as its performance as a channel sounder (extracting detailed directional 5G features in 2,401 beam directions within just 20 ms). We then, for the first time, demonstrate AI-based object classification only using the directional communication features derived by Eye-Beam from ambient mmWave 5G signals transmitted by a gNodeB. Six object classes, including 4 distinct objects concealed in a backpack, are classified with 98% accuracy in an indoor environment.
- 13 June 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal on Selected Areas in Communications
- Vol. 42 (9) , 2354-2368
Eye-Beam: A mmWave 5G-Compliant Platform for Integrated Communications and Sensing Enabling AI-Based Object Recognition
We present Eye-Beam, a programmable platform for integrated communication and sensing. Eye-Beam leverages the hardware and processing required for standard millimeter-wave (mmWave) 5G directional communications to enable sensing functions. Specifically, our platform (1) receives and synchronizes to the data frame of broadcast 5G signals, (2) extracts directional communication features, creating a tensor of spatial information, and (3) utilizes this data as input to a DNN that infers the presence of specific objects in the propagation environment. Eye-Beam includes a programmable 28 GHz 64-element phased array, an SDR, and custom FPGA-based firmware. Eye-Beam’s key capabilities and metrics include (i) synchronization of I/Q data (up to 200 MSPS) with beam steering (among 9,601 beams) with 10 ns accuracy; (ii) a signal processing pipeline that extracts communication features such as the SNR and channel response from received 5G waveforms; and (iii) system orchestration that synchronizes the receiver (RX) to the 5G frame structure of the base station (gNodeB) and maintains it within a worst-case OFDM cyclic prefix of $0.29~\mu $ s. Eye-Beam is also able to emulate gNodeB transmissions. We demonstrate Eye-Beam’s performance by showcasing its communication capability (decoding up to 64-QAM), as well as its performance as a channel sounder (extracting detailed directional 5G features in 2,401 beam directions within just 20 ms). We then, for the first time, demonstrate AI-based object classification only using the directional communication features derived by Eye-Beam from ambient mmWave 5G signals transmitted by a gNodeB. Six object classes, including 4 distinct objects concealed in a backpack, are classified with 98% accuracy in an indoor environment.
- Top Cited Papers
- 27 September 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 57 (12) , 3599-3616
A 24–30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas
We present a 24–30-GHz 256-element dual-polarization transceiver (TRX) phased array based on a 16-element beamformer integrated circuit (BF-IC), 2-element frequency conversion integrated circuit (FC-IC), liquid crystal polymer (LCP)-based combiners and filters, and a tileable package with 64 embedded dual-polarized (dual-pol) antennas. The phased array presented in this work overcomes three key challenges in current 5G millimeter-wave (mmWave) antenna arrays: 1) it supports a dramatic increase in the number of supported fast-access beams; 2) it offers improved power efficiency; and 3) it provides a path to lower solution cost. 1) We enable fast switching among $>$ 30 000 beams—orders of magnitude improvement over prior work—by employing an on-chip beam calculator in the BF-IC, achieving 200-ns beam setup and 8-ns over-the-air (OTA)-switching time. 2) We enable a module-level transmitter (TX) mode peak power added efficiency (PAE) of 20% using a modular architecture that preserves power amplifier (PA) linearity and efficiency as well as receiver (RX) mode low noise amplifier (LNA) noise figure (NF). The module achieves Psat effective isotropically radiated power (EIRP) of 68.5 dBm and BF-IC NF $<$ 3.9 dB. 3) We lower the solution cost by enabling a wider steering range to reduce the number of phased arrays required in a sectorized coverage scheme, by reducing the IC and package area, and by avoiding calibration. The wider steering range is enabled by using an in-package magnetoelectric dipole antenna (for the first time in silicon-based phased arrays), resulting in steering over $\pm$ 70 $^\circ$ in H-and V-pol in both E-and H-planes without requiring any calibration. Moreover, the module achieves $>$ 20-dB cross-polarization isolation across the entire $\pm$ 70 $^\circ$ beam steering range.
- 27 September 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 57 (12) , 3599-3616
Top Cited PapersA 24–30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas
We present a 24–30-GHz 256-element dual-polarization transceiver (TRX) phased array based on a 16-element beamformer integrated circuit (BF-IC), 2-element frequency conversion integrated circuit (FC-IC), liquid crystal polymer (LCP)-based combiners and filters, and a tileable package with 64 embedded dual-polarized (dual-pol) antennas. The phased array presented in this work overcomes three key challenges in current 5G millimeter-wave (mmWave) antenna arrays: 1) it supports a dramatic increase in the number of supported fast-access beams; 2) it offers improved power efficiency; and 3) it provides a path to lower solution cost. 1) We enable fast switching among $>$ 30 000 beams—orders of magnitude improvement over prior work—by employing an on-chip beam calculator in the BF-IC, achieving 200-ns beam setup and 8-ns over-the-air (OTA)-switching time. 2) We enable a module-level transmitter (TX) mode peak power added efficiency (PAE) of 20% using a modular architecture that preserves power amplifier (PA) linearity and efficiency as well as receiver (RX) mode low noise amplifier (LNA) noise figure (NF). The module achieves Psat effective isotropically radiated power (EIRP) of 68.5 dBm and BF-IC NF $<$ 3.9 dB. 3) We lower the solution cost by enabling a wider steering range to reduce the number of phased arrays required in a sectorized coverage scheme, by reducing the IC and package area, and by avoiding calibration. The wider steering range is enabled by using an in-package magnetoelectric dipole antenna (for the first time in silicon-based phased arrays), resulting in steering over $\pm$ 70 $^\circ$ in H-and V-pol in both E-and H-planes without requiring any calibration. Moreover, the module achieves $>$ 20-dB cross-polarization isolation across the entire $\pm$ 70 $^\circ$ beam steering range.
- 1 March 2019
- Published by IBM in IBM Journal of Research and Development
- Vol. 63 (2/3) , 4:1-4:12
Crypto anchors
- 1 March 2019
- Published by IBM in IBM Journal of Research and Development
- Vol. 63 (2/3) , 4:1-4:12
Crypto anchors
- 20 September 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 52 (12) , 3119-3131
A Wide Dynamic Range Buck Converter With Sub-nW Quiescent Power
A buck converter in 65-nm CMOS is optimized for a low quiescent power of 240 pW. It operates with input 1.2–3.3 V and regulates the output from 0.7–0.9 V. Control circuits are designed for low leakage and static current, and scale in power over a hertz to megahertz frequency range, resulting in a wide load current dynamic range of$2\times 10^{6}$ . With a 2-V input, the converter has a peak efficiency of 89% and delivers load currents of 500 pA to 1 mA with efficiency better than 50%. The peak efficiency is 92% for a 1.2-V input.- 20 September 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 52 (12) , 3119-3131
A Wide Dynamic Range Buck Converter With Sub-nW Quiescent Power
A buck converter in 65-nm CMOS is optimized for a low quiescent power of 240 pW. It operates with input 1.2–3.3 V and regulates the output from 0.7–0.9 V. Control circuits are designed for low leakage and static current, and scale in power over a hertz to megahertz frequency range, resulting in a wide load current dynamic range of$2\times 10^{6}$ . With a 2-V input, the converter has a peak efficiency of 89% and delivers load currents of 500 pA to 1 mA with efficiency better than 50%. The peak efficiency is 92% for a 1.2-V input.- 14 July 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 64 (9) , 2582-2590
A Random Linear Network Coding Accelerator in a 2.4GHz Transmitter for IoT Applications
Random linear network coding (RLNC) is an emerging coding technique, which can provide several advantages in wireless networks, such as throughput gains, increased data robustness, and better utilization of network resources. In this paper, we present the first custom VLSI implementation of RLNC, integrated with an ultralow-power 2.4-GHz transmitter. We examine its energy efficiency and error recovery performance in the context of Internet of Things applications, and we perform experiments quantifying its benefits when it operates separately and jointly with physical layer forward error correction (FEC) codes, as a joint channel and network coding scheme. The chip is fabricated in a 65-nm CMOS process, occupies 2 × 1.3 mm2 and consumes 580 pJ/bit for processing and transmitting data at 1 Mbps. The digital packet processor and encoder occupies 200 × 200 μm 2 , consists of an on-chip memory, a multi-rate convolutional encoder, and a RLNC accelerator with configurable redundancy, and consumes 15μW, operating at 0.4 V. For improved spectral efficiency, an on-chip pulse shaping filter is implemented, reducing side lobes by 28 dB while consuming 15μW. According to our over-the-air experiments, RLNC can provide an effective SNR improvement of 5.6 dB when combined with FEC rate 1/2, and 3.4 dB without FEC, at a packet error rate of 10 -2 .
- 14 July 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 64 (9) , 2582-2590
A Random Linear Network Coding Accelerator in a 2.4GHz Transmitter for IoT Applications
Random linear network coding (RLNC) is an emerging coding technique, which can provide several advantages in wireless networks, such as throughput gains, increased data robustness, and better utilization of network resources. In this paper, we present the first custom VLSI implementation of RLNC, integrated with an ultralow-power 2.4-GHz transmitter. We examine its energy efficiency and error recovery performance in the context of Internet of Things applications, and we perform experiments quantifying its benefits when it operates separately and jointly with physical layer forward error correction (FEC) codes, as a joint channel and network coding scheme. The chip is fabricated in a 65-nm CMOS process, occupies 2 × 1.3 mm2 and consumes 580 pJ/bit for processing and transmitting data at 1 Mbps. The digital packet processor and encoder occupies 200 × 200 μm 2 , consists of an on-chip memory, a multi-rate convolutional encoder, and a RLNC accelerator with configurable redundancy, and consumes 15μW, operating at 0.4 V. For improved spectral efficiency, an on-chip pulse shaping filter is implemented, reducing side lobes by 28 dB while consuming 15μW. According to our over-the-air experiments, RLNC can provide an effective SNR improvement of 5.6 dB when combined with FEC rate 1/2, and 3.4 dB without FEC, at a packet error rate of 10 -2 .