Howe Yin Loo
Research Subjects
Howe Yin Loo has a total of 4 co-authors. Here are the top co-authors by number of shared publications:
- Boon Howe Oh
Intel Microelectronics Sdn Bhd, Penang, Malaysia
4 shared publications - Poh Tat Oh
Intel Microelectronics Sdn Bhd, Penang, Malaysia
4 shared publications - Eng Kwong Lee
Intel Microelectronics Sdn Bhd, Penang, Malaysia
3 shared publications Eng Kwong Lee
Intel Microelectronics Sdn Bhd, Bayan Lepas FTZ, P.O. Box 121, 11900 Penang, Malaysia. eng.kwong.lee@intelcom
1 shared publication
Latest Publications
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
The Evolution of CPU Packaging Technology and Future Challenges
The demand for high performance and robustness drive CPU to evolve from MHz to GHz and from single core to multi-core packages. This paper describes the changes in CPU packaging technology and its evolution in the past three decades.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
The Evolution of CPU Packaging Technology and Future Challenges
The demand for high performance and robustness drive CPU to evolve from MHz to GHz and from single core to multi-core packages. This paper describes the changes in CPU packaging technology and its evolution in the past three decades.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Challenges in Stacked CSP Packaging Technology
The electronics industry trend is to offer products that are smaller, with more functionality, better performance and lower cost. Stacked chip scale packaging (CSP) is an innovative packaging technique that involves thinning silicon to enable multiple chips to be stacked in a package for integrated solution. Stacking memory chips and stacking memory and logic chips together are two typical approaches in stacked CSP technology. Combining chips of different sizes is more difficult than adding similar-size chips to a package. Approach in stacked CSP of different die sizes and package configuration will be discussed in this paper.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Challenges in Stacked CSP Packaging Technology
The electronics industry trend is to offer products that are smaller, with more functionality, better performance and lower cost. Stacked chip scale packaging (CSP) is an innovative packaging technique that involves thinning silicon to enable multiple chips to be stacked in a package for integrated solution. Stacking memory chips and stacking memory and logic chips together are two typical approaches in stacked CSP technology. Combining chips of different sizes is more difficult than adding similar-size chips to a package. Approach in stacked CSP of different die sizes and package configuration will be discussed in this paper.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-5
Package Routing and Thermal Analysis on a Multi-Chip Package (MCP)
In today conventional technology, multi-chip packaging (MCP) technology has become more important and popular with the purpose to increase the density of the integrated electronic and processing power. However, increasing in processing speed and enhanced capabilities for high power chip design, thermal management in MCP has become more challenging in heat dissipation due to multiple heat sources. This paper presents the package layout design optimization which plays an important role in ensuring multi chip assembly design rules are met and several approaches to optimize the placement of two dice in a single package will be presented. This paper also illustrates the overview of thermal analysis in MCP to study the effect of balanced and unbalanced power map to the thermal solution of MCP in relation to junction temperature.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-5
Package Routing and Thermal Analysis on a Multi-Chip Package (MCP)
In today conventional technology, multi-chip packaging (MCP) technology has become more important and popular with the purpose to increase the density of the integrated electronic and processing power. However, increasing in processing speed and enhanced capabilities for high power chip design, thermal management in MCP has become more challenging in heat dissipation due to multiple heat sources. This paper presents the package layout design optimization which plays an important role in ensuring multi chip assembly design rules are met and several approaches to optimize the placement of two dice in a single package will be presented. This paper also illustrates the overview of thermal analysis in MCP to study the effect of balanced and unbalanced power map to the thermal solution of MCP in relation to junction temperature.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-5
CPU Package Design Optimization for Performance Improvement and Package Cost reduction
CPU packages continue to undergo significant changes to keep pace with demands of high performance silicon to meet market needs. In the last decades or so, increasingly CPU performance and frequency levels couples with lower product cost have been driving new package technologies. This paper illustrates an approach in CPU package design optimization for performance improvement and package cost reduction through effective capacitor usage and package layer count reduction. This involves the new proposed package stack-up designed to lower packaging cost and as well as mixed type capacitor usage in package power delivery.
- 1 December 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-5
CPU Package Design Optimization for Performance Improvement and Package Cost reduction
CPU packages continue to undergo significant changes to keep pace with demands of high performance silicon to meet market needs. In the last decades or so, increasingly CPU performance and frequency levels couples with lower product cost have been driving new package technologies. This paper illustrates an approach in CPU package design optimization for performance improvement and package cost reduction through effective capacitor usage and package layer count reduction. This involves the new proposed package stack-up designed to lower packaging cost and as well as mixed type capacitor usage in package power delivery.