S. J. Finney
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
S. J. Finney has a total of 23 co-authors. Here are the top co-authors by number of shared publications:
- B. W. Williams
Department of Electronic & Electrical Engineering, Strathclyde University, Glasgow, UK. Royal College Building, 204 George Street, Glasgow G1 1XW, Tel: +44 (0) 141 548 2350, Fax: +44 (0) 141 552 2487
13 shared publications - Khaled Hani Ahmed
Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, U.K.
4 shared publications A.M. Massoud
3 shared publications- Grain Philip Adam
Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, G1 1XW UK
3 shared publications - Ahmed Massoud
Department of Electronic and Electrical Engineering, University of Strathclyde, UK
2 shared publications - Barry W. Williams
Electronic and Electrical Engineering Department University of Strathclyde Glasgow UK
2 shared publications
Latest Publications
- 1 November 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21645256,p. 62-67
Operation of a wye Connected Three-Level Active Power Filter under Non-ideal Conditions
A three-level wye shunt active power filter based on a predictive current controller and line voltage space vector modulation is presented and analyzed. This control scheme treats the non-ideal load as a pure resistive load and compensates the reactive power and harmonics under both ideal and non- ideal conditions, thus the power quality at point of common couplings is improved. Experimental results are presented to demonstrate the effectiveness of this approach, and also reveal the limitation of wye structure APF.
- 1 November 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21645256,p. 62-67
Operation of a wye Connected Three-Level Active Power Filter under Non-ideal Conditions
A three-level wye shunt active power filter based on a predictive current controller and line voltage space vector modulation is presented and analyzed. This control scheme treats the non-ideal load as a pure resistive load and compensates the reactive power and harmonics under both ideal and non- ideal conditions, thus the power quality at point of common couplings is improved. Experimental results are presented to demonstrate the effectiveness of this approach, and also reveal the limitation of wye structure APF.
- 1 November 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1049-1053
Extend the Use of Auxiliary Circuit to Start up, Shut down, and Balance of the Modified Diode Clamped Multilevel Inverter
The diode clamped multilevel inverter (DCMLI) is an attractive high voltage multilevel inverter due to its robustness. The main draw back of the DCMLI is dc link capacitor voltage imbalance. A diode clamped inverter has been used in this research. The method used to balance the dc link capacitors is based on auxiliary switch-mode circuits, which are operated in a discontinuous inductor current mode. This research is focused on how to use auxiliary SMPS circuits to start up, balance, and shutdown the inverter. These functions are an issue in high voltage applications of the multilevel inverter. Simulation and experimental results are presented for the proposed auxiliary circuits operational technique.
- 1 November 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1049-1053
Extend the Use of Auxiliary Circuit to Start up, Shut down, and Balance of the Modified Diode Clamped Multilevel Inverter
The diode clamped multilevel inverter (DCMLI) is an attractive high voltage multilevel inverter due to its robustness. The main draw back of the DCMLI is dc link capacitor voltage imbalance. A diode clamped inverter has been used in this research. The method used to balance the dc link capacitors is based on auxiliary switch-mode circuits, which are operated in a discontinuous inductor current mode. This research is focused on how to use auxiliary SMPS circuits to start up, balance, and shutdown the inverter. These functions are an issue in high voltage applications of the multilevel inverter. Simulation and experimental results are presented for the proposed auxiliary circuits operational technique.
- 1 May 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21669538,p. 1-6
Quasi Two-level Operation of a Five-level Inverter
In this paper a five-level inverter operational mode termed quasi two-level operation is proposed. The multilevel capacitors function in a soft clamping mode where capacitor voltage balancing is maintained by varying the transient dwell time at each level. Two balancing techniques are proposed. The first is based on the selection of suitable resistors to be connected across each dc link capacitor in order to maintain balance. The second method is based on varying the dwell time at the intermediate nodes of the dc link capacitors. The validity of the operational mode and the two proposed balancing techniques are confirmed by simulations and experiments.
- 1 May 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21669538,p. 1-6
Quasi Two-level Operation of a Five-level Inverter
In this paper a five-level inverter operational mode termed quasi two-level operation is proposed. The multilevel capacitors function in a soft clamping mode where capacitor voltage balancing is maintained by varying the transient dwell time at each level. Two balancing techniques are proposed. The first is based on the selection of suitable resistors to be connected across each dc link capacitor in order to maintain balance. The second method is based on varying the dwell time at the intermediate nodes of the dc link capacitors. The validity of the operational mode and the two proposed balancing techniques are confirmed by simulations and experiments.