Xingxuan Huang

Emerging 10 kV silicon carbide (SiC) MOSFET based medium voltage (MV) converters have attracted increasing research interest due to their significantly improved performance compared with silicon (Si) IGBT based converters. The success of such MV converter design requires an accurate model of 10 kV SiC MOSFETs, which is proposed in this paper. The impact of high voltage on the transconductance and the dynamic gate charge characteristics of the 10 kV SiC MOSFET is first characterized. Based on these results, an improved switching model considering high voltage impact is proposed and experimentally verified. The developed model is then applied to aid the design of a 5-level MV flying capacitor converter (FCC). A low-cost decoupling capacitor solution for FCC switching cell is proposed. Challenges posed by high switching speed are examined using the developed model, with a gate resistances selection strategy proposed. Finally, a prototype of the 10 kV SiC device based MV 5L-FCC phase-leg is developed. Its reliable operation under high voltage (e.g., 23 kV) and very fast switching speed (e.g., >100 V/ns) are demonstrated.

This paper presents a desat protection scheme with ultrafast response for high voltage (>3.3 kV) SiC MOSFETs. Its working principle is the same as the conventional desat protection designed for high voltage SiC MOSFETs, yet its blanking time is implemented by fully considering the influence of high negative dv_ds/dt during the fast turn-on transient. With the same circuitry as the conventional desat protection, the proposed protection scheme can significantly shorten the response time of the desat protection when it is used to protect high voltage SiC MOSFETs. In addition, the proposed protection scheme with ultrafast response features strong noise immunity, low-cost, and simple implementation. By taking advantage of the high dv/dt during the normal turn-on transients, the proposed protection scheme can be even faster when the MOSFET has faster switching speed. Design details and the response speed analysis under various short circuit faults are presented in detail. A half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is built to demonstrate the proposed protection scheme. Experimental results at 6.5 kV validate the ultrafast response (115 ns response time under a hard switching fault (HSF), 155 ns response time under a fault under load (FUL)) and strong noise immunity of the proposed desat protection scheme.

Distributed energy resources (DERs) and microgrids have seen tremendous growth and research activities in recent years. Flexible DERs and asynchronous microgrids (ASMG) can have many system-level benefits over fixed DERs and conventional microgrids. The key enabler for flexible DERs and ASMG is a power converter based power conditioning system (PCS) as the interface between DERs/microgrids and the medium voltage (MV) distribution grid. High voltage (HV, >3.3 kV) silicon carbide (SiC) based MV converter is now a promising solution for the PCS. This article presents development and testing of a 10 kV SiC MOSFET based MV PCS for 13.8 kV ASMG. MV PCS converter design addressing high dv/dt issue generated by fast switching of the 10 kV SiC MOSFET is presented. The developed PCS is successfully tested at 25 kV dc 13.8 kV ac voltages and 100 kVA power. Grid support functions are also demonstrated with the developed PCS prototype and hardware tests beds, validating HV SiC converter benefits for ASMG.

The emerging 10 kV SiC MOSFET brings great benefits for medium and high voltage applications, and is drawing increased research attention. Accurate switching transient modeling of the 10 kV SiC MOSFET is critical for successful application. Curve tracer is usually used to extract parameters needed for device modeling. However, the transconductance extracted from curve tracer is tested at low voltage, which is different from the transconductance during actual high voltage turn-on switching transient because of short channel effect and drain induced barrier lowering effect. Moreover, the gate-drain capacitance extracted from curve tracer is tested at static off-state, which is also different from the gate-drain capacitance during dynamic turn-on switching transient as the MOSFET channel is turned on in this process. Conventional models based on curve tracer tests show obvious discrepancies compared to experiments. This paper investigates and characterizes the high voltage transconductance and dynamic gate-drain charge of the 10 kV SiC MOSFET during turn-on switching transient. An improved turn-on switching transient model considering these factors is proposed. Experiments with the 10 kV 20 A SiC MOSFET are conducted and verify the accuracy of the proposed improved model.

This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt . This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs’ switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt , extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

The GaN-based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter with full-line-cycle zero voltage switching (ZVS) is a promising candidate for high-efficiency front-end rectifiers. However, the input current can be degraded by line-cycle current distortion and ac line zero-crossing current spikes, and maintaining reliable ZVS control is difficult in noise-susceptible high-frequency environments. In this paper, a detailed analysis of the current distortion issues in a GaN-based CRM totem-pole PFC with digital ZVS control is provided, and effective approaches are proposed to mitigate different kinds of current distortion and ensure stable ZVS control under high-frequency operation. The proposed solutions have the advantages of straightforward implementation and do not increase the control complexity. The current distortion issues are demonstrated in two GaN-based CRM totem-pole PFC prototypes, a 1.5 kW PFC for data centers and a 100 W PFC in a 6.78 MHz wireless charging power supply for consumer electronics. The proposed methods are experimentally verified with effective mitigation of the current distortion and improvement of the converter power efficiency.

The modular multilevel converter (MMC) is a popular topology in medium- and high-voltage applications, and many efforts have been spent on MMC modeling. However, the impact of submodule voltage sensor noise (SVSN), which becomes more severe due to increasing switching speed of power semiconductors and compact submodule design, has not been considered in conventional models. In this letter, the SVSN is introduced by coupling capacitances between the sensor and power stage in an MMC switching model. Furthermore, the SVSN impact is considered in an MMC average model based on derivation of the relationship between the SVSN and the duty cycle. The proposed MMC switching model and average model considering the SVSN are validated by comparing simulations with experimental results in an MMC prototype using 10-kV SiC MOSFETS.

Using high voltage (HV) Silicon Carbide (SiC) power semiconductors in the modular multilevel converter (MMC) is promising because of a fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulse width modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this paper, limiting the maximum dv/dt to the dv/dt of single power semiconductor and meanwhile maintaining the voltage balance performance. The proposed voltage balancing control is experimentally validated in a 10 kV SiC MOSFET based MMC with four submodules per arm.

This paper presents the characterization of the temperature-dependent short circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) MOSFET. The test platform consisting of a phase-leg configuration and a fast speed 10 kV solid state circuit breaker (SSCB), with temperature control, is introduced in detail. A novel FPGA-based short circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short circuit protection is validated through the platform. The short circuit characteristics for both the hard switching fault (HSF) and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short circuit performance is also presented from 25 °C to 125 °C. The difference of short circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10 kV SiC MOSFET is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short circuit performance.