Tuo Shi

Ferroelectric HfO ₂ memristors are promising for analog conductance control and low-power computing, but stable operation requires polar-phase stabilization and interfacial-transport regulation. Here, using termination-controlled epitaxial Sr-doped HfO ₂ /Nb:SrTiO ₃ (111) heterostructures, we identify localized Ti incorporation and accompanying Ti valence reduction at the TiO ₂ -terminated interface as a mechanism that stabilizes the orthorhombic ferroelectric phase and regulates carrier transport, while hexagonal surface symmetry enables buffer-free epitaxial growth of Sr-doped HfO ₂ . The films exhibit a remanent polarization of 41.2 µC cm ^− 2 and an estimated full polarization of 71 µC cm ^− 2 along [001], approaching the predicted limit for Sr-doped hafnia. The corresponding devices sustain 10 ¹⁰ switching cycles and expand the number of programmable conductance states in ferroelectric hafnia memristors to 1,104. As application-level validation of this high-resolution conductance modulation, these stable analog states support high-fidelity in-memory inverse discrete Fourier transform image reconstruction and a 27-device lightweight fuzzy controller for robotic obstacle avoidance. Enabled by ~ 2.4 fJ single-device readout, a projected fully parallel implementation reaches 130.57 pJ per inference, more than two orders of magnitude below conventional CMOS fuzzy ASICs. This work establishes symmetry-guided interface engineering as a route to high-performance ferroelectric memristors for compact, energy-efficient analog computing.

Analog computing-in-memory devices leverage fundamental physical laws for computation, greatly enhancing energy efficiency. However, the stochastic characteristics of analog devices conflict with the deterministic weight update of the backpropagation algorithm (BP), limiting training performance. To overcome the algorithm-device mismatch, we propose an error-aware probabilistic update method (EaPU) that updates the weights based on a specified probability derived from device writing noise. Compared to BP, EaPU reduces the number of weight updates to <1‰ with minimal performance loss. Furthermore, we validate EaPU experimentally on a 180 nm memristor system for image denoising and super-resolution and simulate its performance on ResNet and Vision Transformers. Results confirm that EaPU training yields over 60% accuracy improvement, with ~50.54× and 13.23× lower training energy (and ~35.51× and 11.26× lower inference energy) compared to BP-based memristor training and MADEM, respectively. Moreover, EaPU-based memristor hardware reduces training energy by nearly 6 orders of magnitude compared to graphics processing units. Here, we present a promising approach to precisely and efficiently train analog device-based deep neural networks.

The ferroelectricity in nanoscale HfO₂-based films enables their applications more promising than that of the perovskite oxides, taking into account the easy compatibility with the modern silicon-based semiconductor technology. However, the well-known polar orthorhombic phase is thermodynamically metastable, making the applications of HfO₂-based ferroelectrics challenging in terms of uncontrollability and consequently instability of the physical performance in electronic devices. Here we report the robust ferroelectricity in stable monoclinic Hf_0.5Zr_0.5O₂ single-crystalline films, which was known as non-polar before. The as-prepared films display high endurance performance of wake-up free and non-fatigue behavior up to 10¹² cycles. Multimode imaging under aberration-corrected scanning transmission electron microscopy reveals that such an unexpected ferroelectric behavior is resultant from an antiphase boundaries-derived monoclinic polar variant (space group, Pc) intergrown with the nonpolar monoclinic phase (P2₁/c). The switching barrier for the stable polar variant is only 20~50% of that for the metastable orthorhombic phase according to the calculation by the nudged elastic band method. These findings provide a practical approach for designing robust ferroelectricity in hafnia-based materials and would be helpful for the development of lower energy-cost and long-life memory devices compatible with integrated circuit technology.

Parallel and energy-efficient searching of the shortest paths on a large graph is challenging. Conventional methods commonly used are sequential and computing intensive, rendering them inadequate for addressing large-scale and real-time situations. Here, we propose a highly parallel, computation- and energy-efficient approach to shortest path–based graph learning based on an emerging memristor spiking neural network via algorithm-device codesign. The shortest path is obtained parallelly in nature using simultaneous spike traveling instead of arithmetic calculation, achieving extremely low time and space complexity. A nonlinear weight mapping approach is proposed to counterbalance the neuron intrinsic nonlinearity to guarantee accuracy to support large-scale graphs. The memristor hardware capability is experimentally demonstrated in unsupervised and supervised classification tasks. The estimated energy efficiency of 517.82 giga-traversal edges per second per watt outperforms field programmable gate arrays by three to four orders of magnitude, providing a pathway toward highly energy-efficient graph computing hardware.

Inspired by biological processes, feature learning techniques, such as deep learning, have achieved great success in various fields. However, since biological organs may operate differently from semiconductor devices, deep models usually require dedicated hardware and are computation-complex. High energy consumption has made deep model growth unsustainable. We present an approach that directly implements feature learning using semiconductor physics to minimize disparity between model and hardware. Following this approach, a feature learning technique based on memristor drift-diffusion kinetics is proposed by leveraging the dynamic response of a single memristor to learn features. The model parameters and computational operations of the kinetics-based network are reduced by up to 2 and 4 orders of magnitude, respectively, compared with deep models. We experimentally implement the proposed network on 180 nm memristor chips for various dimensional pattern classification tasks. Compared with memristor-based deep learning hardware, the memristor kinetics-based hardware can further reduce energy and area consumption significantly. We propose that innovations in hardware physics could create an intriguing solution for intelligent models by balancing model complexity and performance.

Neuro-symbolic artificial intelligence has garnered considerable attention amid increasing industry demands for high-performance neural networks that are interpretable and adaptable to previously unknown problem domains with minimal reconfiguration. However, implementing neuro-symbolic hardware is challenging due to the complexity in symbolic knowledge representation and calculation. We experimentally demonstrated a memristor-based neuro-fuzzy hardware based on TiN/TaO_x/HfO_x/TiN chips that is superior to its silicon-based counterpart in terms of throughput and energy efficiency by using array topological structure for knowledge representation and physical laws for computing. Intrinsic memristor variability is fully exploited to increase robustness in knowledge representation. A hybrid in situ training strategy is proposed for error minimizing in training. The hardware adapts easier to a previously unknown environment, achieving ~6.6 times faster convergence and ~6 times lower error than deep learning. The hardware energy efficiency is over two orders of magnitude greater than field-programmable gate arrays. This research greatly extends the capability of memristor-based neuromorphic computing systems in artificial intelligence.

Neuromorphic computing based on spike neural networks (SNNs) exhibits great potential in reducing energy consumption in hardware systems. Resistive random-access memory (ReRAM) is regarded as a promising candidate to construct neuromorphic hardware, attributing to their high-density, nonvolatile, and compute-in-memory capability. However, the ReRAM-based neuromorphic chips are still in their infancy, cannot support multicore or with limited neuron configurability. To alleviate these problems, we propose a hybrid multicore SNN chip based on 60 K-ReRAM synapses and 480-digital neurons in the 180 nm node, achieving a synaptic density of 20K bit/mm ² per core. To improve the efficiency of inter-core communication, we adopt a network-on-chip architecture with a bit character encoding strategy. In addition, an adaptive multiplier-less digital neuron is designed to support both Izhikevich and leaky integrate-and-fire models through register bit control, meeting different application scenarios. Finally, we evaluate the performance of our chip on the MNIST dataset recognition tasks, achieving 97.65% accuracy. Also, a minimum energy per synaptic operation (SOP) of 6.6 pJ in the 180 nm node is obtained, outperforming the TrueNorth’s 26 pJ in 28 nm. These results show that our design has a great potential for large-scale SNN implementations and may pave the way for designing high-efficient neuromorphic hardware with ReRAM technology.

Neuromorphic computing aims to achieve artificial intelligence by mimicking the mechanisms of biological neurons and synapses that make up the human brain. However, the possibility of using one reconfigurable memristor as both artificial neuron and synapse still requires intensive research in detail. In this work, Ag/SrTiO₃(STO)/Pt memristor with low operating voltage is manufactured and reconfigurable as both neuron and synapse for neuromorphic computing chip. By modulating the compliance current, two types of resistance switching, volatile and nonvolatile, can be obtained in amorphous STO thin film. This is attributed to the manipulation of the Ag conductive filament. Furthermore, through regulating electrical pulses and designing bionic circuits, the neuronal functions of leaky integrate and fire, as well as synaptic biomimicry with spike-timing-dependent plasticity and paired-pulse facilitation neural regulation, are successfully realized. This study shows that the reconfigurable devices based on STO thin film are promising for the application of neuromorphic computing systems.