Giorgos Fagas

In this review, we focus on group IV one-dimensional devices for quantum technology. We outline the foundational principles of quantum computing before delving into materials, architectures and fabrication routes, separately, by comparing the bottom-up and top-down approaches. We demonstrate that due to easily tunable composition and crystal/interface quality and relatively less demanding fabrications, the study of grown nanowires such as core–shell Ge-Si and Ge hut wires has created a very fruitful field for studying unique and foundational quantum phenomena. We discuss in detail how these advancements have set the foundations and furthered realization of SETs and qubit devices with their specific operational characteristics. On the other hand, top-down processed devices, mainly as Si fin/nanowire field-effect transistor (FET) architectures, showed their potential for scaling up the number of qubits while providing ways for very large-scale integration (VLSI) and co-integration with conventional CMOS. In all cases we compare the fin/nanowire qubit architectures to other closely related approaches such as planar (2D) or III–V qubit platforms, aiming to highlight the cutting-edge benefits of using group IV one-dimensional morphologies for quantum computing. Another aim is to provide an informative pedagogical perspective on common fabrication challenges and links between common FET device processing and qubit device architectures.

A new technological approach is needed for the development of emerging electronic components and systems within the Internet of Things (IoT) era. New advancements and innovations are required in architectural design and hybrid systems heterogeneous integration to address the challenge of widespread IoT deployment, its power demands and sustainability. Hybrid chips are one of the emerging technologies that can help overcome the current limitations in terms of energy consumption, performance and sustainability that could shape the future of electronic systems for targeted applications. Hybrid chips combine different materials and manufacturing technologies on the same substrate or package using advanced flexible heterogeneous integration techniques, with the focus of merging the advantages of each unit or technology toward enhanced performance and new levels of emerging functionalities. The categorization of hybrid chips spans across rigid hybrid chips that follow a multi-chiplet approach, semi-flexible chips that integrate flexible units with semi-rigid ones such as thinned silicon integrated circuits, and lastly, flexible chips in which all components are inherently flexible. This perspective article analyzes technical challenges that arise concerning the development of sustainable materials and processing technologies, complex heterogeneous integration, as well as advanced packaging architectures, standardization, and reliability testing. The economic implications for the semiconductor technology transition to hybrid chips is presented in terms of manufacturing costs, economic feasibility, and market readiness. Key insights and future application opportunities are provided, while recent advancements in the field are summarized. This perspective article suggests that by addressing these challenges, hybrid chips have the potential to transform electronic components and systems across a wide range of industries and use case scenario. The advancement of hybrid chip technologies by enhancing the collaboration between industry and academia as well as policymakers will be a crucial part in the realization of required sustainability goals within the worldwide Chips Act initiative, while ensuring the technological progress has the right balance between improved performance and sustainability.

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects I_ON-I_OFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between I_ON and I_OFF for digital logic in advanced technology nodes.

Empirical complex potentials are often used to model interactions between bound states and continua. These interactions can also be modeled by the self-energy. We discuss the relation between complex potentials and the self-energy, using the latter to construct a non-local, ab initio complex potential. We apply our scheme to studying transmission in an atomic chain, obtaining excellent agreement with the exact result.

Energy Challenges for ICT | InTechOpen, Published on: 2017-03-22. Authors: Giorgos Fagas, John P. Gallagher, Luca Gammaitoni, et

Alkyl monolayer modified Si forms a class of inorganic–organic hybrid materials with applications across many technologies such as thin-films, fuel/solar-cells and biosensors. Previous studies have shown that the linker atom, through which the monolayer binds to the Si substrate, and any tail group in the alkyl chain, can tune the monolayer stability and electronic properties. In this paper we study the H:Si(111) surface functionalized with binary SAMs: these are composed of alkyl chains that are linked to the surface by two different linker groups. Aiming to enhance SAM stability and increase coverage over singly functionalized Si, we examine with density functional theory simulations that incorporate vdW interactions, a range of linker groups which we denote as –X–(alkyl) with X = CH₂, O(H), S(H) or NH₍₂₎ (alkyl = C₆ and C₁₂ chains). We show how the stability of the SAM can be enhanced by adsorbing alkyl chains with two different linkers, e.g. Si–[C, NH]–alkyl, through which the adsorption energy is increased compared to functionalization with the individual –X–alkyl chains. Our results show that it is possible to improve stability and optimum coverage of alkyl functionalized SAMs linked through a direct Si–C bond by incorporating alkyl chains linked to Si through a different linker group, while preserving the interface electronic structure that determines key electronic properties. This is important since any enhancement in stability and coverage to give more densely packed monolayers will result in fewer defects. We also show that the work function can be tuned within the interval of 3.65–4.94 eV (4.55 eV for bare H:Si(111)).

As the diameter of semimetal nanowires decreases semimetal to semiconductor transition occurs as a consequence of quantum confinement. This enables the use of bandgap engineering to form a field-effect transistor near atomic dimensions and eliminates the need for doping in the transistor's source, channel, or drain for sub-5 nm transistors. The use of strain as a `technology booster' in transistor design has been used in Si technology; in this study the electronic structure of tin nanowires (SnNW) under uniaxial strain is investigated using density functional theory (DFT). Also, the valence and conduction charge density modification under applying uniaxial strain is studied. It is demonstrated that the properties of a 4.2 nm [110]-oriented SnNW varies towards more metallic or semiconducting by the application of tensile or compressive strain, respectively. Strain energies and Young modulus which vary with nanowire diameter and crystal orientation are also analysed. It is demonstrated that strain can be applied in addition to geometry confinement to tune the bandgap and other electronic properties.