Rafael Domínguez-Castro

High-speed imagers are required for industrial applications, traffic monitoring, robotics and unmanned vehicles, moviemaking, etc. Many of these applications call also for large spatial resolution, high sensitivity and the ability to detect images with large intra-frame dynamic range. This paper reports a CIS intelligent digital image sensor with 5.2Mpixels which delivers 12-bit fully-corrected images at 250Fps. The new sensor embeds on-chip digital processing circuitry for a large variety of functions including: windowing; pixel binning; sub-sampling; combined windowing-binning-subsampling modes; fixed-pattern noise correction; fine gain and offset control; color processing, etc. These and other CIS functions are programmable through a simple four-wire serial port interface.

This paper describes a Vision-System-on-Chip (VSoC) capable of doing: image acquisition, image processing through on-chip embedded structures, and generation of pertinent reaction commands at thousand's frame-per-second rate. The chip employs a distributed processing architecture with a pre-processing stage consisting of an array of programmable sensory-processing cells, and a post-processing stage consisting of a digital microprocessor. The pre-processing stage operates as a retina-like sensor front-end. It performs parallel processing of the images captured by the sensors which are embedded together with the processors. This early processing serves to extract image features relevant to the intended tasks. The front-end incorporates also smart read-out structures which are conceived to transmit only these relevant features, thus precluding full gray-scale frames to be coded and transmitted. The chip is capable to close action-reaction loops based on the analysis of visual flow at rates above 1,000F/s with power budget below 1W peak. Also, the incorporation of processors close to the sensors enables signal-dependent, local adaptation of the sensor gains and hence highdynamic range signal acquisition.

We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by exploiting bio-inspiration and performing processing tasks in parallel manner and concurrently with image acquisition. A vision system is presented which makes decisions within sub-msec range. This is very well suited for defense and security applications requiring segmentation and tracking of rapidly moving objects.

This demo illustrates the processing capabilities of the Eye-RIS vision systems; specifically using the Eye-RIS v1.2. These systems employ an AnaFocus's a proprietary architecture where processing is realized in two steps. The first stage of the architecture embeds sensors, parallel processing analog and mixed-signal circuitry, control circuitry and memory. This front-stage is implemented through dedicated bio-inspired chips. The second stage of the Eye-RIS vision system architecture is a digital microprocessor. The combination of parallel preprocessing and serial post-processing makes the Eye-RIS systems very efficient particularly the Eye-RIS systems are capable to close the sensor-processing-actuation loop at a high speed. In this demo, the Eye-RIS v1.2 is used to recognize data matrix codes at more than 200 codes/sec rate.

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

Some features of the biological retina can be modelled by a 2-layer cellular neural network (CNN) composed of locally connected elementary nonlinear processors. In order to explore these complex spatiotemporal dynamics for image processing, a prototype chip has been designed and fabricated in a 0.5μm CMOS technology. Design challenges, trade-offs, the building blocks and the tests results for this system with 0.5×10⁶ transistors, most of them operating in analog mode, are presented in this paper.

This paper presents the architecture of the Elementary Processing Unit — EPU — which has been employed to design a CNN-Based 128×128 Focal Plane Mixed-Signal Microprocessor for vision. The EPU contains the required building blocks to implement, on chip, vision algorithms based on the execution of linear 3×3 convolution masks,¹ or information propagative CNN templates.² Using this EPU, we have designed a prototype, called ACE16k, which contains an array of 128×128 EPUs and a completely digital interface, in a standard fully-digital 0.35 μm CMOS technology. The estimation results forecast 300 GOPS, 3.23 GOPS/mm² and 100 GOP/J.