Joel Gak

This paper presents a case study conducted at a university in Uruguay, where a Computer Engineering student explored Fractal Geometry through the design and performance analysis of fractal antennas based on the Sierpinski triangle iterations 2 and 3. The research began in a linear algebra course that is part of the curriculum for several Engineering programs (Agronomy, Food Engineering, Electronics, Computer Science, Artificial Intelligence, Telecommunications) and extended into an introductory research project. The study focused on characteristic properties of fractals, such as self-similarity, non-integer fractal dimension, and having an infinite perimeter within a finite area, which facilitated the design of small multiband antennas. From the student’s work, it was observed that interpreting and validating the studied concepts through the analysis of fractal antenna performance completed a modeling cycle, as the findings demonstrated advantages of these antennas over traditional ones. This allowed for the experimental validation of theoretical models, strengthening the connection between Mathematics and its applications, and highlighting the educational value of integrating theory and experimentation in the learning of Fractal Geometry.

In this work, a custom integrated circuit, aimed at implementing a low-cost radio-frequency identification (RFID) reader for the livestock industry, fully compliant with the international organization for standardization (ISO) 11784/5 standard @134.2 kHz for animal ID is presented. First, the reader-tag link was characterized. Then, an initial version of the analog RFID front-end was implemented using discrete electronic components, and tested. Using these measurement results, a second mixed-signal version of the RFID reader engine was designed to be implemented in an application-specific integrated circuit (ASIC); this version includes a preamplifier, an optimized analog to digital converter (ADC), digital filters, HV driver, and complementary circuits. The complete circuit was designed in a 0.18 ${\mu \text{m}}$ complementary metal-oxide-semiconductor (CMOS)-high voltage (HV) technology, including the analog front-end and programmable digital infinite impulse response filters, that can be adapted for both half-duplex and full-duplex ISO11784/5 RFID tags. The resulting circuit occupies an area $< {1.0 \,\text{mm}^{2}}$.

In this work, the power management (PM) system to drive long range wide area network (LoRaWAN) latching solenoid valves (LSVs) for automated irrigation systems is studied in detail. The objective is to optimize the use of a supercapacitor and a boost converter, allowing to drive the LSVs from a small primary battery, even a button cell, to reduce installation costs and battery environmental impact issues. Two different LSVs were analyzed, one requiring a 12 V-1 A high-current pulse to be activated, while the second one requires a 9 V-1.8 A pulse. Detailed supercapacitor, converter, and leakage measurements are presented, allowing to properly optimize the circuit design and PM system. Following the proposed guidelines, a wireless solenoid valve can be operated for five years from a single 1/2AA LiSOCl₂ primary battery.

In this work, modeling, simulation, and experimental measurements of a LoRaWAN network aimed at implementing a dense farm-area network (FAN) in the agrifood industry are presented. First, the network is modeled for a farm of the future, with as many sensors as would be useful, for the four main productive chains in Uruguay as a study case: livestock, timber, agriculture, and dairy industries. To this end, a survey of commercial sensors was conducted, a few farms were visited, and managers and partners in agrocompanies were interviewed. A LoRaWAN network with a single gateway was simulated to estimate the efficiency (related to data packets lost), in the case of a 1000 ha cattle field with more than 1500 sensors and some cameras sharing the network. Finally, the network efficiency was measured, using 30–40 LoRa modules @ 915 MHz, transmitting at pseudorandom times to emulate up to thousands of LoRa sensor nodes. The simulated and measured results are very similar, reaching > 92% efficiency in all cases. Sites bigger than 1000 ha on the four main productive chains were also simulated. Additionally, energy consumption and transmission distance measurements of LoRaWAN modules are presented, as well as an overview of the economic aspects related to the deployment of the network to corroborate them fit the requirements of a FAN in the agribusiness.

Open-source tools and PDKs facilitate the design, implementation and silicon validation of integrated circuits, circumventing the traditional barriers associated with this field. Power integrated circuits, conversely, are increasingly relevant in modern systems targeting energy-efficient applications. In this study, the design of a power integrated circuit is examined from the perspective of open-source silicon design, which has recently emerged as a feasible approach for acquiring functional silicon-proven designs with low entry barriers. Utilizing this workflow, we showcase the complete design, simulation, layout, and experimental validation of an integrated multilevel dc-dc converter: specifically, a three-level flying capacitor buck converter. Our system converts 3.3V dc bus levels to 1.8V and below, for a measured peak efficiency of 89.3%. The maximum measured load current is 250mA, using two conversion cores operating in interleaved mode. The system has been implemented in 6.27mm ² of active area using the Skywater 130nm standard CMOS technology open-source PDK.

Summary: In this work, a self‐configuration system and the frequency characterization for a fully integrated CMOS photodetector sensor is presented. The sensor is composed of pixels with programmable switches that allow each pixel to connect with its neighbors; in this way, an arbitrary detection pattern can be synthesized on it. The design was aimed to be part of an optical encoder based on a non‐diffractive light beam; therefore, the purpose of the self‐configuration routine is to find the center of the incident non‐diffractive beam and then configure the detection pattern around it. The corresponding algorithm is implemented on a Zynq‐7000SoCallowing to automate the alignment of the beam with the detection pattern, without using micrometric positioning procedures. The frequency response of the analog front‐end of the entire chip (the pixels and the amplification system) is addressed via SPICE simulations and experimental data and is consistent with the classical mathematical models, allowing us to propose future improvements to the design.