Luca Sterpone
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Luca Sterpone has a total of 335 co-authors. Here are the top co-authors by number of shared publications:
- Matteo Sonza Reorda
Department of Control and Computer Engineering, Politecnico di Torino, Turin, Italy
44 shared publications M. Violante
DAUIN, Politecnico di Torino, Turin, Italy
33 shared publications- Corrado De Sio
Politecnico di Torino
31 shared publications - Sarah Azimi
Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy
30 shared publications Massimo Violante
Politecnico di Torino, Italy
22 shared publications- Boyang Du
Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy
21 shared publications
Latest Publications
- Open Access
- 25 September 2026
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 98 (2) , 48
A Novel Schematic–Layout Co-Analysis Framework for Selective Radiation Hardening in Nanoscale Technology
Technology scaling in nanoscale FinFET technologies increases circuit susceptibility to radiation-induced single event effects (SEEs). This work proposes a schematic–layout co-analysis and selective hardening framework for radiation-aware circuit design. The methodology combines LET-based fault injection at the schematic level with three-dimensional layout-aware particle strike simulation to identify the most vulnerable nodes and their corresponding sensitive physical regions. Guided by this analysis, selective hardening strategies are applied to improve radiation resilience with minimal overhead. The framework is validated on three representative circuits implemented in FreePDK15 technology: a 2:1 MUX, a multi-supply level shifter, and a D flip-flop. Experimental results show that the proposed approach increases the minimum $$LET_{\textrm{th}}$$ of the Multiplexer (MUX), level shifter, and D-Flip-Flop (DFF) by $$38\mathrm {MeV\cdot cm^2/mg}$$ , $$18\mathrm {MeV\cdot cm^2/mg}$$ , and $$12\mathrm {MeV\cdot cm^2/mg}$$ , respectively. In addition, the hardened designs reduce the SET cross-section for all the case studies, especially, by nearly one order of magnitude for the level shifter, while maintaining moderate implementation overhead. These results demonstrate the effectiveness of the proposed framework for overhead-efficient radiation-aware design in advanced FinFET circuits.- 25 September 2026
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 98 (2) , 48
Open AccessA Novel Schematic–Layout Co-Analysis Framework for Selective Radiation Hardening in Nanoscale Technology
Technology scaling in nanoscale FinFET technologies increases circuit susceptibility to radiation-induced single event effects (SEEs). This work proposes a schematic–layout co-analysis and selective hardening framework for radiation-aware circuit design. The methodology combines LET-based fault injection at the schematic level with three-dimensional layout-aware particle strike simulation to identify the most vulnerable nodes and their corresponding sensitive physical regions. Guided by this analysis, selective hardening strategies are applied to improve radiation resilience with minimal overhead. The framework is validated on three representative circuits implemented in FreePDK15 technology: a 2:1 MUX, a multi-supply level shifter, and a D flip-flop. Experimental results show that the proposed approach increases the minimum $$LET_{\textrm{th}}$$ of the Multiplexer (MUX), level shifter, and D-Flip-Flop (DFF) by $$38\mathrm {MeV\cdot cm^2/mg}$$ , $$18\mathrm {MeV\cdot cm^2/mg}$$ , and $$12\mathrm {MeV\cdot cm^2/mg}$$ , respectively. In addition, the hardened designs reduce the SET cross-section for all the case studies, especially, by nearly one order of magnitude for the level shifter, while maintaining moderate implementation overhead. These results demonstrate the effectiveness of the proposed framework for overhead-efficient radiation-aware design in advanced FinFET circuits. - 3 July 2026
- Published by Springer Nature
- p. 162-176
Reinforcing Local Safety Ecosystems: Integrating the “Signal for Help” Detection in Urban and Inner Territories
- 3 July 2026
- Published by Springer Nature
- p. 162-176
Reinforcing Local Safety Ecosystems: Integrating the “Signal for Help” Detection in Urban and Inner Territories
- Open Access
- 19 May 2026
- Published by Association for Computing Machinery (ACM)
- p. 230-234
Reliability Analysis of TMR Configurations in SRAM-Based FPGAs Using Static Evaluation
- 19 May 2026
- Published by Association for Computing Machinery (ACM)
- p. 230-234
Open AccessReliability Analysis of TMR Configurations in SRAM-Based FPGAs Using Static Evaluation
- Open Access
- 19 May 2026
- Published by Association for Computing Machinery (ACM)
- p. 331-332
POSTER: A Reliable Multi-FPGA RISC-V Based Cluster for Space AI Inference
- 19 May 2026
- Published by Association for Computing Machinery (ACM)
- p. 331-332
Open AccessPOSTER: A Reliable Multi-FPGA RISC-V Based Cluster for Space AI Inference
- Open Access
- 19 May 2026
- Published by Association for Computing Machinery (ACM)
- p. 67-70
Robust Quantum Communication for Space Systems Through an Heterogeneous RISC-V based FPGA/SoC Platform
- 19 May 2026
- Published by Association for Computing Machinery (ACM)
- p. 67-70
Open AccessRobust Quantum Communication for Space Systems Through an Heterogeneous RISC-V based FPGA/SoC Platform
- 11 May 2026
- Published by Springer Nature in Space Science Reviews
- Vol. 222 (4) , 49
The Hera Milani Mission: Use of a Nanosatellite for Planetary Defence Purposes
- 11 May 2026
- Published by Springer Nature in Space Science Reviews
- Vol. 222 (4) , 49
The Hera Milani Mission: Use of a Nanosatellite for Planetary Defence Purposes
- Open Access
- 1 April 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 19 (3) , 1-34
Fast SEU Detection and Recovery in FPGA-Based AI Accelerators
Heterogeneous FPGA platforms combining RISC-V processors and deep-learning accelerators are increasingly adopted in avionics and space, where performance must be paired with fault tolerance. We present RePAIR, a reconfigurable platform integrating an open-source RISC-V core with a TPU-like systolic-array accelerator for runtime fault detection, correction, and recovery. RePAIR extends the accelerator ISA with runtime self-test, enabling detection of structural faults in the array during inference. The platform supports dual inference modes: a plain mode with no overhead and a testing mode that performs checksum validation at a fixed cost of three extra cycles per matrix multiplication, with limited accelerator area overhead. Upon fault detection, the accelerator notifies the RISC-V processor, which triggers dynamic partial reconfiguration of the faulty region while preserving execution state, allowing inference to resume from the last correct step. Compared with full-device reconfiguration, recovery time is reduced by up to 900× on AMD KCU105 and 1400× on AMD ZCU102, while inference overhead remains ≤30% in the worst case. The methodology is hardware-agnostic and portable across FPGA devices, as shown by multi-platform implementations. Fault-injection campaigns combined with space-environment modeling estimate mean time to failure under mission conditions, demonstrating scalable and reliable FPGA-based AI acceleration for safety-critical applications.
- 1 April 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 19 (3) , 1-34
Open AccessFast SEU Detection and Recovery in FPGA-Based AI Accelerators
Heterogeneous FPGA platforms combining RISC-V processors and deep-learning accelerators are increasingly adopted in avionics and space, where performance must be paired with fault tolerance. We present RePAIR, a reconfigurable platform integrating an open-source RISC-V core with a TPU-like systolic-array accelerator for runtime fault detection, correction, and recovery. RePAIR extends the accelerator ISA with runtime self-test, enabling detection of structural faults in the array during inference. The platform supports dual inference modes: a plain mode with no overhead and a testing mode that performs checksum validation at a fixed cost of three extra cycles per matrix multiplication, with limited accelerator area overhead. Upon fault detection, the accelerator notifies the RISC-V processor, which triggers dynamic partial reconfiguration of the faulty region while preserving execution state, allowing inference to resume from the last correct step. Compared with full-device reconfiguration, recovery time is reduced by up to 900× on AMD KCU105 and 1400× on AMD ZCU102, while inference overhead remains ≤30% in the worst case. The methodology is hardware-agnostic and portable across FPGA devices, as shown by multi-platform implementations. Fault-injection campaigns combined with space-environment modeling estimate mean time to failure under mission conditions, demonstrating scalable and reliable FPGA-based AI acceleration for safety-critical applications.
- Open Access
- 15 March 2026
- Published by Elsevier in SSRN Electronic Journal
SCALES: A Distributed k-NN Architecture for Embedded Systems
The increasing availability of embedded systems has opened up new opportunities for distributed machine learning, where multiple low-cost boards can collaborate to execute complex algorithms, providing high performance at a lower cost. Traditional centralized algorithms, such as k-Nearest Neighbors (k-NN), often scale poorly when datasets are large or computational resources are limited. We propose SCALES (SCAlable cLassification on Embedded Systems), a framework that enables a distributed platform for k-NN classification using clusters of embedded devices. Our approach enables parallel execution, reducing computational time while preserving accuracy. The framework is designed to be flexible and plug-and-play, supporting various numbers of nodes and data partitioning strategies. We validated SCALES on both real-world and synthetic datasets of various sizes and dimensions. We systematically compared multiple data partitioning strategies, including random split, k-means, and balanced k-means. Experimental results demonstrate that distributed k-NN on embedded clusters significantly reduces execution time while preserving classification accuracy. Among the evaluated strategies, balanced k-means achieves the most effective trade-off between execution time and classification accuracy.
- 15 March 2026
- Published by Elsevier in SSRN Electronic Journal
Open AccessSCALES: A Distributed k-NN Architecture for Embedded Systems
The increasing availability of embedded systems has opened up new opportunities for distributed machine learning, where multiple low-cost boards can collaborate to execute complex algorithms, providing high performance at a lower cost. Traditional centralized algorithms, such as k-Nearest Neighbors (k-NN), often scale poorly when datasets are large or computational resources are limited. We propose SCALES (SCAlable cLassification on Embedded Systems), a framework that enables a distributed platform for k-NN classification using clusters of embedded devices. Our approach enables parallel execution, reducing computational time while preserving accuracy. The framework is designed to be flexible and plug-and-play, supporting various numbers of nodes and data partitioning strategies. We validated SCALES on both real-world and synthetic datasets of various sizes and dimensions. We systematically compared multiple data partitioning strategies, including random split, k-means, and balanced k-means. Experimental results demonstrate that distributed k-NN on embedded clusters significantly reduces execution time while preserving classification accuracy. Among the evaluated strategies, balanced k-means achieves the most effective trade-off between execution time and classification accuracy.
- Open Access
- 25 February 2026
- Published by Elsevier in Intelligent Systems with Applications
- Vol. 30
A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration
- 25 February 2026
- Published by Elsevier in Intelligent Systems with Applications
- Vol. 30
Open AccessA novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration
- 2 January 2026
- Published by Springer Nature
- p. 314-326
Fault Tolerant Multi-object Tracking via Temporal Consistency Filtering
- 2 January 2026
- Published by Springer Nature
- p. 314-326
Fault Tolerant Multi-object Tracking via Temporal Consistency Filtering