Jb Begueret

An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type oscillators. These excellent performances come at the expense of a very poor integration density. To alleviate this issue, this work introduces an injection-locked ring oscillator-based PLL circuit. The combination of the injection-locking process with the use of ring oscillators allows for the benefit of excellent jitter performance while presenting an extremely low surface area due to an architecture without any inductor. The injection locking principle is addressed, and evidence of its phase noise and jitter improvements are confirmed through measurement results. Indeed, phase noise and jitter enhancements up to 43 dB and 23.3 mUI, respectively, were measured. As intended, this work shows the best integration density compared to recent similar state-of-the-art studies. The whole architecture measures 0.1 mm² while consuming 34.6 mW in a low-cost 180 nm CMOS technology.

Summary: In high‐speed serial links, the data rates reach the multigigabits per second, and continue to increase. Jitter is 1 of the most important parameters used to characterize high‐speed serial link performances. Generating white and colored noise synthetic jitter patterns would allow to better analyze the effect of jitter in a system for design verification. The standard organizations give separated budgets for random and deterministic jitter. Being able to model the phase noise of the different components of SerDes, generating corresponding time jitter, and decomposing it into deterministic and random jitter would help designers to better specify future SerDes systems. In our knowledge, there has been proposed no other study until today presenting a complete tutorial about jitter, its definition, its relation with phase noise, how to generate different white or colored noise patterns, and how to decompose random from deterministic jitter. This paper presents for the first time a complete study about jitter, by giving its definition, its relation with phase noise, and information on how to measure the jitter in the frequency and time domain. Furthermore, a new method for generating Gaussian distribution synthetic jitter patterns from colored noise profiles is presented. A novel technique of jitter decomposition into random and deterministic jitter is given. This technique is validated with generated and measured jitter patterns.

Summary: With the reduction of the supply voltage in modern complementary metal‐oxide‐semiconductor technologies, and by their intrinsic class AB behavior, inverter‐based amplifiers are suitable to replace classical operational transconductance amplifiers in switched capacitor circuits like sigma‐delta modulators. This paper presents a new inverter‐based amplifier which increases the reliability versus process, voltage, and temperature variations. A new biasing stage is proposed, which controls the bias current without losing the class AB behavior thanks to the use of biasing transistors operated in linear region and a slew rate enhancement circuit. This makes this amplifier more robust than simple inverters regarding to process, voltage, and temperature variations, reducing the worst‐case bias current spread from +140% to +20%, while costing only 15% consumption increase and keeping inverter dynamic strengths.

Summary: When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f²phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.

A millimeter-wave (mmW) chipset for 77-81 GHz automotive radar has been developed in 0.13μm SiGe HBT technology. This work presents the performances of an integrated Low Noise Amplifier (LNA), a Power Amplifier (PA), a down-converting Mixer, and also a Voltage Controlled Oscillator (VCO). For successful implementation of the circuit, considerations on the reliability of the design have been taken into account. Measurements on all circuits confirm the feasibility of mmW front-end using silicon based technologies for W-band application.

This paper describes VCO designs based on varactor tuned Push-Push architecture. Two versions (powered under 1.2V and 1.8V) of the 79GHz oscillators have been designed in a 0.13mum SiGe BiCMOS technology, thus targeting automotive Radar and millimeter-wave applications. Their tuning ranges are respectively set on 6GHz (7.6%) and 7GHz (8.8%). The oscillator cores solely consume 18mW and 30mW, and both achieve low phase noise characteristics -102dBc/Hz at 1MHz offset from the carrier frequency (80GHz) and output powers of -18dBm and 0dBm respectively.

Implemented in a 0.25 mum SiGe technology, a 5.2 GHz Injection Locked Oscillator (ILO) for Radio-Frequency (RF) applications is shown to be intrinsically radiation-hardened. Design principles and laser-based testing results are presented