Rolf Drechsler
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Rolf Drechsler has a total of 541 co-authors. Here are the top co-authors by number of shared publications:
- Robert Wille
Technical University of Munich
117 shared publications - Daniel Große
Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria
93 shared publications Robert Wille
Johannes Kepler University Linz, Linz, Austria
38 shared publications- Mathias Soeken
Integrated Systems Laboratory, EPFL
36 shared publications Mathias Soeken
Integrated Systems Laboratory, EPFL
33 shared publicationsJannis Stoppe
German Res Ctr Artificial Intelligence DFKI GmbH, Inst Comp Sci, D-28359 Bremen, Germany
22 shared publications
Latest Publications
- Open Access
- 21 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Design Automation of Electronic Systems
The Deception of Sight: Camouflaging Chips Information Against Optical Probing Attacks By Selective Increase of Local Density
In recent years, a novel non-invasive laser-assisted attack known as Optical Probing (OP) has been demonstrated to effectively probe the internal state of integrated circuits. This attack exploits the relative transparency of the silicon substrate to Near-InfraRed (NIR) light, enabling optical access through the backside of the chip. Consequently, OP poses a significant threat to information processed or stored on the chip and may facilitate Intellectual Property (IP) theft or reverse engineering. Existing mitigation techniques can be broadly classified into three categories: (1) fabrication-level modifications, (2) sensor-based countermeasures, and (3) circuit-level design techniques. Fabrication-based countermeasures are costly and often incompatible with standard industrial manufacturing processes, limiting their practicality for OP-resilient chip design. Sensor-based countermeasures may be circumvented by adaptive attackers, whereas circuit-level techniques typically require modifications to the layout of standard-cell libraries. Such modifications are time-consuming and can introduce considerable PPA overheads relative to conventional standard-cell designs. Therefore, this study investigates whether increasing the local layout density around a target logic cell can enhance resilience against OP attacks without requiring modifications beyond the layout level. In this context, local density refers to the fraction of a predefined region surrounding the target cell that is occupied by neighboring logic cells and associated layout structures. Our methodology employs standard logic cells to protect the chip’s sensitive information from an adversary equipped with OP capabilities. We found that increasing the local density of surrounding logic cells near a target logic cell enhances overall reflection, effectively masking the reflection from the target logic cell. This can significantly improve the concealment of the secure cell’s information from the OP attack since the reflections from the neighboring logic cells overlap with the target logic cells that need to be secured. Hence, an adversary cannot distinguish the exact location of the source of reflection. We demonstrate that this methodology can effectively countermeasure against OP attacks by conducting detailed experiments on the relationship between density and reflection, using NAND, INVERTER, NOR, and Flip-Flop cells. We exhaustively evaluated thousands of placement strategies with varying densities to show the efficacy of our technique against OP attacks. Moreover, we demonstrate the integration of our OP attack mitigation technique into the ASIC flow for designing an AES-128 core. We demonstrate that our technique in the worst-case comes with a 1% increase in power consumption, a 1% increase in area, and no change in the operating frequency compared to the unprotected AES-128 core against OP attack.
- 21 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Design Automation of Electronic Systems
Open AccessThe Deception of Sight: Camouflaging Chips Information Against Optical Probing Attacks By Selective Increase of Local Density
In recent years, a novel non-invasive laser-assisted attack known as Optical Probing (OP) has been demonstrated to effectively probe the internal state of integrated circuits. This attack exploits the relative transparency of the silicon substrate to Near-InfraRed (NIR) light, enabling optical access through the backside of the chip. Consequently, OP poses a significant threat to information processed or stored on the chip and may facilitate Intellectual Property (IP) theft or reverse engineering. Existing mitigation techniques can be broadly classified into three categories: (1) fabrication-level modifications, (2) sensor-based countermeasures, and (3) circuit-level design techniques. Fabrication-based countermeasures are costly and often incompatible with standard industrial manufacturing processes, limiting their practicality for OP-resilient chip design. Sensor-based countermeasures may be circumvented by adaptive attackers, whereas circuit-level techniques typically require modifications to the layout of standard-cell libraries. Such modifications are time-consuming and can introduce considerable PPA overheads relative to conventional standard-cell designs. Therefore, this study investigates whether increasing the local layout density around a target logic cell can enhance resilience against OP attacks without requiring modifications beyond the layout level. In this context, local density refers to the fraction of a predefined region surrounding the target cell that is occupied by neighboring logic cells and associated layout structures. Our methodology employs standard logic cells to protect the chip’s sensitive information from an adversary equipped with OP capabilities. We found that increasing the local density of surrounding logic cells near a target logic cell enhances overall reflection, effectively masking the reflection from the target logic cell. This can significantly improve the concealment of the secure cell’s information from the OP attack since the reflections from the neighboring logic cells overlap with the target logic cells that need to be secured. Hence, an adversary cannot distinguish the exact location of the source of reflection. We demonstrate that this methodology can effectively countermeasure against OP attacks by conducting detailed experiments on the relationship between density and reflection, using NAND, INVERTER, NOR, and Flip-Flop cells. We exhaustively evaluated thousands of placement strategies with varying densities to show the efficacy of our technique against OP attacks. Moreover, we demonstrate the integration of our OP attack mitigation technique into the ASIC flow for designing an AES-128 core. We demonstrate that our technique in the worst-case comes with a 1% increase in power consumption, a 1% increase in area, and no change in the operating frequency compared to the unprotected AES-128 core against OP attack.
- 23 September 2026
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 98 (2) , 46
Hardware Non-Idealities and Reliability in RRAM Crossbar Neuromorphic Character Recognition Systems
- 23 September 2026
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 98 (2) , 46
Hardware Non-Idealities and Reliability in RRAM Crossbar Neuromorphic Character Recognition Systems
- 1 September 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 423-430
Forging Robust Building Blocks for Next-Gen RISC-V Chips: Virtual Repository and IP Card
- 1 September 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 423-430
Forging Robust Building Blocks for Next-Gen RISC-V Chips: Virtual Repository and IP Card
- 1 September 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 350-358
Scalability Matters: Future-Proof Formal Verification of a RISC-V Arithmetic Logic Unit
- 1 September 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 350-358
Scalability Matters: Future-Proof Formal Verification of a RISC-V Arithmetic Logic Unit
- 21 August 2026
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 98 (2) , 41
Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing
- 21 August 2026
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 98 (2) , 41
Multi-Scheduling Crossbar Mapping and Design-Space Exploration of MAGIC-Based ReRAM Arithmetic Circuits for In-Memory Computing
- 2 August 2026
- Published by Springer Nature
- p. 1-15
Polynomial Representation of Rounded Floating-Point Addition Using *PHDDs
- 2 August 2026
- Published by Springer Nature
- p. 1-15
Polynomial Representation of Rounded Floating-Point Addition Using *PHDDs
- Open Access
- 13 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1135-1143
Can Explainability Metrics Improve Genetic Programming? Lessons from 2048
Genetic programming (GP) produces solutions that, while often less performant than neural networks, are uniquely amenable to analysis. In domains like game-playing, this explainability could reveal why certain policies succeed or fail—but such insights are rarely leveraged to improve the algorithms themselves. Here, we analyze a GP algorithm for 2048, testing whether structural, behavioral, or semantic metrics of evolved policies correlate with performance. While structural metrics showed no predictive power and behavioral features yielded ambiguous results, we identified a semantic feature that correlated with policy quality. Using this insight, we designed a mutation operator that improved performance. Though modest, this improvement suggests that explainability metrics can guide operator design, even when broader explanatory goals remain unmet. More broadly, our work highlights a potential advantage of GP: its solutions may be analyzable in ways that opaque methods like neural networks are not.
- 13 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1135-1143
Open AccessCan Explainability Metrics Improve Genetic Programming? Lessons from 2048
Genetic programming (GP) produces solutions that, while often less performant than neural networks, are uniquely amenable to analysis. In domains like game-playing, this explainability could reveal why certain policies succeed or fail—but such insights are rarely leveraged to improve the algorithms themselves. Here, we analyze a GP algorithm for 2048, testing whether structural, behavioral, or semantic metrics of evolved policies correlate with performance. While structural metrics showed no predictive power and behavioral features yielded ambiguous results, we identified a semantic feature that correlated with policy quality. Using this insight, we designed a mutation operator that improved performance. Though modest, this improvement suggests that explainability metrics can guide operator design, even when broader explanatory goals remain unmet. More broadly, our work highlights a potential advantage of GP: its solutions may be analyzable in ways that opaque methods like neural networks are not.
- Open Access
- 13 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1499-1502
Enhancing Surrogate Model Usability for Optimisation Experts through Extended ML Support in EvoAl
- 13 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1499-1502
Open AccessEnhancing Surrogate Model Usability for Optimisation Experts through Extended ML Support in EvoAl
- Open Access
- 13 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1491-1494
Ride-Sharing Simulation for Optimisation
- 13 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1491-1494
Open AccessRide-Sharing Simulation for Optimisation
- Open Access
- 29 June 2026
- Published by IOS Press
- Vol. 338, 524-528
Simulation-Based Hardware Exploration for Shapley Value Calculations
Shapley values are a popular method used to explain the output of machine learning models. They proved to be an important tool for providing trustworthy machine learning systems in healthcare. However, their exact computation is computationally expensive. Various approximation methods have been proposed, often implemented in high level programming languages such as Python. In this work, efficient computations of Shapley values on RISC-V based systems and specialized hardware are explored. Following recent trends of quantized neural networks, an implementation compatible with fixed point implementations is proposed. Using a virtual prototype, the different implementations of Shapley value calculations are benchmarked for different RISC-V ISA extensions and compared to a simulated hardware implementation for quantized Shapley values.
- 29 June 2026
- Published by IOS Press
- Vol. 338, 524-528
Open AccessSimulation-Based Hardware Exploration for Shapley Value Calculations
Shapley values are a popular method used to explain the output of machine learning models. They proved to be an important tool for providing trustworthy machine learning systems in healthcare. However, their exact computation is computationally expensive. Various approximation methods have been proposed, often implemented in high level programming languages such as Python. In this work, efficient computations of Shapley values on RISC-V based systems and specialized hardware are explored. Following recent trends of quantized neural networks, an implementation compatible with fixed point implementations is proposed. Using a virtual prototype, the different implementations of Shapley value calculations are benchmarked for different RISC-V ISA extensions and compared to a simulated hardware implementation for quantized Shapley values.