Eby G. Friedman

Reliable timing is a crucial issue in all synchronous systems. Delay locked loops are capable of dynamically synchronizing clock signals; the increasing speed of deeply scaled technologies however leads to long and complex delay lines. In this paper, a sawtooth-based delay locked loop is proposed to address the increasing difficulty of delay generation in high speed systems. The proposed architecture replaces a conventional delay line with a sawtooth waveform-based mechanism for delay generation, reducing the need for numerous delay elements. The timing offset is mapped to a voltage level on the sawtooth waveform, where the required delay is the time to cross this voltage level. The architecture, evaluated using a 7 nm device model, achieves a locking speed as low as four cycles for a 1 GHz clock signal. The DLL achieves a full period locking range, lowers the clock skew to 16 ps at room temperature, and exhibits 65 ps clock skew variations over extreme temperature corners.

Systems requiring multiple clock frequencies are becoming more common in digital superconductive electronics. In rapid single flux quantum circuits, precise frequencies are applied to different clock domains. A diverse variety of SFQ clock generators have been employed to produce a single frequency. A clock generator that uses a single voltage source to deliver multiple frequencies is presented here. The operating principle, performance, area, and power of the proposed SFQ multiclock generator are described. Previously published clock generators are limited to a fixed frequency or varied by changing the bias dc voltage—a parameter not typically changed in situ. In the proposed approach, the clock frequency is tunable by the SFQ logic circuit. In addition, a GALS system is presented to exemplify the practical application of the proposed multiclock generator.

High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under nonideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes ac-to-dc converters, introducing area and complexity overhead. This work proposes an alternative method for applying ac biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for ac-to-dc converters. This approach also combines resistive dc biasing with inductive ac biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5% . The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.

A multiplexer is a digital structure that controls signal flow, selecting among multiple inputs to produce a single output. A two-input to one output (2:1) multiplexer is commonly used in single flux quantum (SFQ) systems. When three or more inputs to one output are required, 2:1 SFQ multiplexers are typically cascaded to create a multiplexer tree. A multi-input SFQ multiplexer comprising both a three-input (3:1) and four-input (4:1) to one output SFQ multiplexer is presented. These multiplexers require fewer control signals without cascading multiple 2:1 multiplexers. This SFQ circuit function is achieved using an XOR gate, AND gate, NOR gate, non-destructive read out cells, splitters, and confluence buffers for the 3:1 multiplexer. The XOR gate in the 3:1 multiplexer is replaced with two gates that distinguish between the 01 and 10 control signals. The circuit topologies are presented, and the performance and control signals are compared with a conventional 2:1 multiplexer tree and an individual input control multi-input multiplexer. A combination of 2:1, 3:1, and 4:1 multiplexers is proposed to achieve higher performance, leveraging the advantages of each type of multiplexer. A speed increase of 36% and an 83.6% reduction in the number of control signals in a 54:1 multi-input SFQ multiplexer are demonstrated using the combined multiplexer tree.

As single flux quantum (SFQ) circuit complexities scale, larger bias currents are required. The large current produces excessive heat and greatly complicates the design process. Current recycling offers a solution by reducing the required bias current through serially biased circuit blocks. Serial biasing is typically achieved in homogeneous SFQ systems where similar bias currents are required in similar circuits. Each of these homogeneous circuits is often placed on different ground planes and serially biased to reuse the bias currents. To address heterogeneous circuits with varying bias current requirements, a novel serial biasing technique is proposed. An interface between the ground planes with unequal bias current is presented that exhibits a current balancing capability. The interface supplies additional current before passing the current to the next ground plane. The ground planes are arranged in ascending order of bias current to manage the complexity of these heterogeneous circuits. Using a one bit SFQ full adder as an example, the proposed approach demonstrates several key benefits: a 49% reduction in the number of driver-receiver pairs, a 6.5% reduction in power dissipation, and a 35% reduction in bias current across a heterogeneous SFQ circuit placed on three isolated ground planes. The performance, bias current margins, and methods for current reduction are also discussed, showcasing the effectiveness of current recycling in improving the efficiency of complex heterogeneous SFQ systems.

A multiply-accumulator, often abbreviated as a MAC unit, is central to a multitude of computational tasks, particularly those tasks (such as neural networks) involving array-based mathematical computations. The quest for novel methods to efficiently store and process data in a MAC has become imperative. Recently, ternary logic has attracted significant attention due to its higher information density than conventional binary systems. However, though numerous studies have showcased ternary arithmetic circuits, advancements in ternary-based vector processing have been notably scarce. To bridge this gap, this work undertakes comprehensive study into the optimization of ternary MAC units. Firstly, we propose various ternary approximate algorithms which shows 30%-less power consumption and only 2% computation error when compared with the accurate design. Secondly, we design sophisticated ternary circuits and obtain 74% $\sim$ 80% lower power-delay-product (PDP) than previous works. Finally, we evaluate the proposed ternary MAC unit using both carbon-nanotube field-effect transistor (CNTFET) and silicon-based 180 nm CMOS processes. The simulation results show the ternary circuit is better than binary circuit in terms of both area ( $\sim$ 45% less) and power ( $\sim$ 30% less), highlighting its strong potential for practical applications.

Power delivery in three-dimensional (3-D) integrated systems poses several challenges such as high current densities, large voltage drops due to multiple levels of resistive vertical interconnect, and significant switching noise originating from transient currents within different layers. Voltage stacking is a power delivery technique that is highly compatible with 3-D integration due to the physical proximity between layers, enabling the efficient transfer of recycled current. Power noise in clock networks is, however, not inherently addressed by 3-D voltage stacking. In this brief, a quasi-adiabatic technique between multiple clock networks within 3-D voltage stacked systems is proposed. The technique exploits the proximity of the clock networks to enable mutual charging and discharging when the clock signals transition to the same voltage. During this transition, the clock distribution networks are isolated from the power grid, reducing simultaneous switching noise and current load. The maximum current is reduced by an additional 13% as compared to only voltage stacking, the maximum voltage noise is reduced by up to 72% when the clock networks are isolated from the power grids, and the clock networks pull nearly 50% less charge from the source. The proposed technique is evaluated on a 7 nm predictive technology model.