Xuefei Li

The development of high-performance p-type monolayer transistors is critical for extending two-dimensional (2D) semiconductors beyond silicon in sub 1-nm technology nodes for complementary metal–oxide–semiconductor (CMOS) circuits. However, insufficient doping and metal-induced gap states (MIGS) during metal deposition lead to high contact resistance, greatly limiting p-type on-state currents. Here, we demonstrate high-performance ballistic p-type monolayer tungsten diselenide (WSe ₂ ) transistors by oxygen p-doping. The controllable oxygen doping greatly reduces the number of Se vacancy defects in as-grown WSe ₂ , and thus increases the hole mobility from 55 to 218.3 cm ² V ⁻¹ s ⁻¹ —approaching the theoretical limit. Moreover, this approach also induces a heavily hole-doped contact region in p-type monolayer WSe ₂ devices and decreases the contact resistance from 1869 Ω·μm down to 104 Ω·μm. Consequently, a 16-nm-channel WSe ₂ p-type field effect transistor (pFET) delivers a saturation current of up to 1635 μA μm ⁻¹ at a drain voltage of −1.2 V and a ballistic ratio as high as 81% at room temperature.

In this work, we report a method to improve the trade-off between the breakdown voltage (BV) and specific on-resistance (R_ON,sp) of top-gate amorphous indium gallium oxide (IGO) high-voltage thin-film transistors (HV TFTs) with selective F plasma treatment for offset regions. X-ray photoelectron spectroscopy (XPS) confirmed that F plasma treatment effectively increased the oxygen vacancy (V_O) concentration in the IGO film, improving the conductivity of the offset regions. Accordingly, the offset-region resistance of top-gate HV IGO TFTs is reduced by 58.3%, while its pristine threshold voltage (V_TH) of -2.2 V and subthreshold swing (SS) of 81 mV/dec are preserved. Specifically, the top-gate HV IGO TFT with L_GD = 10 μm achieves a high BV of 1015 V and an R_ON,sp of 79 mΩ·cm². Our results show the great potential of top-gate HV IGO TFTs in high-voltage and high-power applications.

Artificial Intelligence (AI), has been occupying the central position in recent technological advancement, propelled by exponentially increasing computing resources, which in turn stimulate the demand on higher level 3D integration for integrated circuits. However, current frontside-only integration is inevitably bottlenecked by the routing congestion and parasitic degradation on the wafer frontside, blocking the further down scaling. Fortunately, the underutilized backside space of wafer provides inimitable opportunities to break this blockage. Here, we demonstrate the "Flip 3D" (F3D) technology which utilizes both sides of wafer to capture the ultra-high-density connectivity of monolithic integration while maintaining the architectural flexibility of heterogeneous integration. F3D technology enables the co-integration of logic, memory, and connectivity with significantly reduced interconnect parasitics. Experimentally, F3D technology was verified on a FinFET test vehicle in a dual-sided form, successfully integrating logic, temperature sensors, optical modules, on-chip memory, and high-density computing-in-memory cells. We further introduce "Hyper 3D" (H3D) technology for dual-sided system-on-wafer integration. Our results validate that this unified dual-sided scheme provides effective solution to the "computing," "memory," and "connectivity" walls. This work establishes a scalable roadmap for multi-layer on-chip systems, providing a full-3D hardware strategy for the next generation of AI hardware.

The rapid development of generative artificial intelligence is driving the growing demand for high‐capacity dynamic random‐access memory (DRAM). Amorphous oxide semiconductor‐based 2T0C DRAM has garnered considerable attention for its potential in overcoming the scaling limitations of conventional 1T1C DRAM. However, inherent stability issues have hindered device performance and practical adoption. In this work, high performance and excellent bias stability in ultrathin indium‐gallium‐oxide (IGO) field‐effect transistors through O ₃ ‐based HfO ₂ passivation is demonstrated. This improvement results from the suppression of shallow‐level defects, deep‐level oxygen vacancies, and hydrogen impurities, leading to a high field‐effect mobility of 35 cm ² V ⁻¹ s ⁻¹ , a positive threshold voltage, and outstanding stability—exhibiting only a +5‐mV threshold voltage shift under −5 MV cm ⁻¹ bias for 1 h. The resulting 2T0C DRAM cell achieves a retention time of over 30 000 s—a 100 × improvement over unpassivated devices—together with a 10 ns write speed, 4‐bit storage capability, and endurance exceeding 10 ¹¹ cycles, representing a viable platform for future high‐density memory applications.

Two-dimensional ferroelectric tunnel junctions (2D FTJs) have attracted extensive attention in recent years, which mainly change the height of the tunnel barrier via manipulation of the ferroelectric polarization. However, it is very challenging to realize the high tunneling electroresistance (TER) of FTJs based on the barrier height. Here, we report the 2D FTJs using a unique structure with semiconducting MoS₂/α-In₂Se₃/monolayer graphene, where ferroelectric polarization of α-In₂Se₃ shifts the barrier height by 1.05 eV. More importantly, the MoS₂ dynamically tunes the barrier width, overcoming traditional barrier height limitations and enhancing TER by an order of magnitude. The dual modulation of barrier width and height yields a giant TER of more than 1 × 10⁹ at room temperature. In addition, the FTJs possess excellent retention time for up to 10 years. This study exhibits that the constructed 2D FTJs have unprecedented applications in achieving high-performance memory, electronic, optoelectronic, and neuromorphic computing devices.

In this work, we investigate the physical origin of hydrogen (H) stability at high temperature of atomic-layer-deposited (ALD) indium-gallium-zinc oxide (IGZO) transistors with different passivation stacks. The hydrogen stability of ALD IGZO transistors is found to be determined by the interfacial oxygen vacancy (V_O) generation due to the broken of In-O bonds during passivation layer growth and the formation of substitutional H in V_O (H_O) during high-temperature annealing in H-rich environment. Device fabrication process is optimized including silicon dioxide (SiO₂) passivation growth with O-rich process and post-annealing engineering. As a result, we demonstrate ALD IGZO transistors with passivation achieving a V_TH change of 9 mV after forming gas annealing (FGA, 4% H₂/96% N₂) at 400 ^∘C. Meanwhile, we also demonstrate ALD IGZO transistors without passivation achieving a V_TH change of 0.13 V after FGA at 450 ^∘C. Our work suggests suppressing V_O generation is critical to enhance the H stability of ALD IGZO transistors.