Donald S. Gardner

This paper presents the Quick Error Detection (QED) technique for systematically creating families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory controllers, and on-chip interconnection networks) of multicore system on chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of traditional post-silicon validation approaches. QED can be implemented completely in software, without any hardware modification. Hence, it is readily applicable to existing designs. Results using multiple hardware platforms, including the Intel® Core™ i7 SoC, and a state-of-the-art commercial multicore SoC, along with simulation results using an OpenSPARC T2-like multicore SoC with bug scenarios from commercial multicore SoCs demonstrate: 1) error detection latencies of post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs inside uncore components; 2) QED shortens error detection latencies by up to nine orders of magnitude to only a few hundred cycles for most bug scenarios; and 3) QED enables up to a fourfold increase in bug coverage.

In this paper, soft ferromagnetic materials were deposited on organic packaging substrates to explore their potential applications in in-package inductors. Amorphous cobalt alloy, Co-Zr-Ta-B, was chosen due to its high saturation magnetization, low coercivity and small magnetostriction. As-deposited films were characterized by vibrating sample magnetometer (VSM) showing comparable magnetic properties in comparison to the films on quartz and silicon wafers. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on package substrates to explore their potential in-package RF and power inductor applications.

In this paper, the role of the magnetic vias for magnetic flux and eddy current control is investigated using both simulations and experiments that used different patterning techniques and by altering the magnetic via width. Improved finger-shaped magnetic vias have been designed and integrated into on-chip radio frequency inductors improving the peak quality factor from 400 MHz to 800 MHz without sacrificing the inductance enhancement. The eddy currents and magnetic flux density in different areas of the magnetic vias are analyzed by 3D electromagnetic simulation. With optimized magnetic vias, the high frequency response of up to 2 GHz has been achieved.

The saturation field of patterned amorphous Co-Zr-Ta-B films is adjusted by using shape anisotropy in patterned magnetic thin films for inductors. The relationship between aspect ratio and saturation field which is essential for achieving high saturation current in magnetic inductors is investigated. By changing the aspect ratio of patterned films, the in-plane easy and hard axes induced during film deposition gradually decrease and then change direction as the aspect ratio is changed, which is also verified by numerically calculating the demagnetizing field in the films. It is shown that the saturation field of inductors with patterned Co-Zr-Ta-B films can be changed thus, providing a pathway towards high saturation current in high power density applications such as voltage regulators.

In this work, we report the improvement of high frequency response and quality factor of on-chip inductors by integrating ferromagnetic thin films (Co-Zr-Ta-B) including two different combinations of laminations and 500 nm thick non-laminated film. Up to 4.2X increase in inductance and 5X increase in quality factor (Q) was obtained from 4-turn spiral inductors incorporated with 50 nm by 10 laminated films with a peak Q at 500 MHz. Effects of patterning magnetic film have also been investigated by changing magnetic thin film aspect ratio. It was demonstrated that the peak Q can be pushed towards using higher frequencies as high as 1 GHz by a combination of patterning magnetic films into fine bars and laminations.

Existing post-silicon validation techniques are generally ad hoc, and their cost and complexity are rising faster than design cost. Hence, systematic approaches to post-silicon validation are essential. Our research indicates that many of the bottlenecks of existing post-silicon validation approaches are direct consequences of very long error detection latencies. Error detection latency is the time elapsed between the activation of a bug during post-silicon validation and its detection or manifestation as a system failure. In our earlier papers, we created the Quick Error Detection (QED) technique to overcome this significant challenge. QED systematically creates a wide variety of post-silicon validation tests to detect bugs in processor cores and uncore components of multi-core System-on-Chips (SoCs) very quickly, i.e., with very short error detection latencies. In this paper, we present an overview of QED and summarize key results: 1. Error detection latencies of “typical” post-silicon validation tests can range up to billions of clock cycles. 2. QED shortens error detection latencies by up to 6 orders of magnitude. 3. QED enables 2- to 4-fold improvement in bug coverage. QED does not require any hardware modification. Hence, it is readily applicable to existing designs. Author(s) Lin, David Department of EE, Stanford University, CA, USA Hong, Ted ; Li, Yanjing ; Fallah, Farzan ; Gardner, Donald S. ; Hakim, Nagib ; Mitra, Subhasish

Integrated on-chip inductors with boron-incorporated amorphous Co-Zr-Ta-B films for reducing the size of the inductor and increasing the quality factor are presented. A 3.5-fold increase in inductance and a 3.9-fold increase in quality factor over inductors without magnetic films are measured at frequencies as high as 1 GHz. The Co-Zr-Ta-B films are patterned into the shape of fingers in the magnetic via region to improve the on-chip inductors, high frequency response. Compared with nonpatterned films, finger-shaped magnetic vias result in at least a 30% increase in quality factor in the gigahertz range. It is also demonstrated that by using laminations, an up to 9.1X inductance increase with good frequency response up to 2 GHz can be achieved.

This article consists of a collection of slides from the author's conference presentation on the deployment of integrated inductors with magnetic materials for on-chip power conversion. Some of the specific topics discussed include: the special features and processing capabilities of DC voltage converters; the properties of magnetic materials; and key features and processing capabilities of inductors.