Normann Mertig

We demonstrate high-fidelity single qubit control in a natural Si-MOS quantum dot fabricated in an industrial 300 mm wafer process on a silicon on insulator wafer using electron spin resonance. A relatively high optimal Rabi frequency of 5 MHz is achieved, decoupling the electron spin from its 29Si environment. Tracking the qubit frequency reduces the impact of low-frequency noise in the qubit frequency and improves the TRabi from 7 to 11 μs at a Rabi frequency of 5 MHz, resulting in Q-factors exceeding 50. Randomized benchmarking returns an average single gate control fidelity of 99.5±0.3%. As a result of pulse-area calibration, this fidelity is limited by the Rabi Q-factor. These results show that a fast Rabi frequency and a feedback protocol enable high fidelity in these Si-MOS devices, despite the low-frequency magnetic noise.

Adaptive variational quantum eigensolvers (ADAPT-VQEs) are promising candidates for simulations of strongly correlated systems on near-term quantum hardware. To further improve the noise resilience of these algorithms, recent efforts have been directed towards compactifying, or layering, their Ansatz circuits. Here, we broaden the understanding of the algorithmic layering process in three ways. First, we investigate the noncommutation relations between the different elements that are used to build ADAPT-VQE Ansätze. In doing so, we develop a framework for studying and developing layering algorithms, which produce shallower circuits. Second, based on this framework, we develop a new subroutine that can reduce the number of quantum-processor calls by optimizing the selection procedure with which a variational quantum algorithm appends Ansatz elements. Third, we provide a thorough numerical investigation of the noise-resilience improvement available via layering the circuits of ADAPT-VQE algorithms. We find that layering leads to an improved noise resilience with respect to amplitude-damping and dephasing noise, which, in general, affect idling and nonidling qubits alike. With respect to depolarizing noise, which tends to affect only actively manipulated qubits, we observe no advantage of layering.

Inspired by the challenge of scaling-up existing silicon quantum hardware, we propose a 2d spin-qubit architecture with low compilation overhead. The architecture is based on silicon nanowire split-gate transistors which form 1d chains of spin-qubits and allow the execution of two-qubit operations among neighbors. We introduce a silicon junction which can couple four nanowires into 2d arrangements via spin shuttling andSwapoperations. We then propose a modular sparse 2d spin-qubit architecture with unit cells of diagonally-oriented squares with nanowires along the edges and junctions on the corners. Targeting noisy intermediate-scale quantum (NISQ) demonstrators, we show that the proposed architecture allows for compilation strategies which outperform methods for 1d chains, and exhibits favorable scaling properties which enable trading-off compilation overhead and colocation of control electronics within each square by adjusting the nanowire length. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes.

Minor embedding heuristics have become an indispensable tool for compiling problems in quadratically unconstrained binary optimization (QUBO) into the hardware graphs of quantum and CMOS annealing processors. While recent embedding heuristics have been developed for annealers of moderate size (about 2000 nodes) the size of the latest CMOS annealing processor (with 102,400 nodes) poses entirely new demands on the embedding heuristic. This raises the question, if recent embedding heuristics can maintain meaningful embedding performance on hardware graphs of increasing size. Here, we develop an improved version of the probabilistic-swap-shift-annealing (PSSA) embedding heuristic [which has recently been demonstrated to outperform the standard embedding heuristic by D-Wave Systems (Cai et al., 2014)] and evaluate its embedding performance on hardware graphs of increasing size. For random-cubic and Barabasi-Albert graphs we find the embedding performance of improved PSSA to consistently exceed the threshold of the best known complete graph embedding by a factor of 3.2 and 2.8, respectively, up to hardware graphs with 102,400 nodes. On the other hand, for random graphs with constant edge density not even improved PSSA can overcome the deterministic threshold guaranteed by the existence of the best known complete graph embedding. Finally, we prove a new upper bound on the maximal embeddable size of complete graphs into hardware graphs of CMOS annealers and show that the embedding performance of its currently best known complete graph embedding has optimal order for hardware graphs with fixed coordination number.

QBoost is a recently proposed machine learning algorithm, designed to exploit the benefits of emerging annealing processors which solve NP hard problems in combinatorial optimization a hundred times faster than conventional CPUs. In this paper, we present the first FPGA-based implementation of QBoost, incorporating a large-scale annealing processor with 2704 spins. In contrast to previous implementations, based on quantum annealers, we utilize the flexibility of FPGAs for implementing a fast, integrated QBoost engine which combines the annealing processor and the modules of the hyperparameter search on a single FPGA. As opposed to quantum annealers, this accelerates the time required for scanning the hyperparameter space from the order of hours to a single second.