Rongshan Wei

To address the challenges posed by DC electrode offset, motion artifacts, and high electrode‐skin contact impedance to the input range and conversion accuracy of analog front ends (AFEs) for electroencephalography (EEG) acquisition, this paper presents a third‐order discrete‐time Δ‐ΔΣ direct‐digitization AFE. The proposed architecture employs a noninverting pseudo‐differential instrumentation amplifier, switched‐capacitor integrators, a 4‐bit successive‐approximation‐register (SAR) quantizer, and a digital accumulator (ACC). By subtracting the differential input voltages at two adjacent sampling instants, first‐order shaping of the input signal is achieved, thereby reducing the dynamic‐range (DR) requirement imposed by DC offsets and low‐frequency interference. Data‐weighted averaging (DWA) is employed to suppress unit‐mismatch errors in the multibit feedback DAC. The circuit is designed and laid out in a 180‐nm CMOS process and verified through post‐simulation. It operates at a sampling frequency of 1 MHz with a 1.8 V supply and consumes 1.07 mW. Post‐simulation results show that, with an 800‐mVpp differential input, the AFE achieves an SNDR of 96.13 dB and an SNR of 97.42 dB, and an input‐referred noise of approximately 3.8 μVrms over a 4‐kHz bandwidth. The SNDR‐based figure of merit FoM _SNDR is 161.9 dB, and the system achieves a DR of approximately 100.73 dB. The input impedance is 3.367 GΩ at 100 Hz and remains 84.57 MΩ at 4 kHz. The proposed AFE achieves high conversion accuracy, a wide input range, and high input impedance, making it suitable for electroencephalography (EEG) acquisition.

This article presents a discrete-time, third-order, single-loop, 17-level delta-sigma modulator (DSM) for high-dynamic-range sensor measurement applications, which employs a loop filter auto-shift (LFAS) technique. It uses an on-chip 1.5-bit Schmitt monitor to determine whether the input amplitude is large or small. The DSM automatically shifts to loop filter A for large input amplitudes to achieve a larger maximum stable amplitude (MSA) and shifts to loop filter B for small input amplitudes to reduce equivalent kT/C noise and in-band quantization noise (IBQN). The 1.5-bit successive-approximation-register (SAR) monitor, 17-level SAR quantizer, false trigger protection (FTP) module, capacitor compensation array, and pre-charge cascoded floating inverter amplifier (PFIA) support real-time shifting of the proposed DSM while ensuring good performance. The prototype DSM is designed and fabricated in a 180-nm CMOS process, achieving a 101.1-dB SNDR and a 108.3-dB dynamic range (DR) within a 3-kHz bandwidth, while consuming $18.3~\mu $ W. With the help of the LFAS technique, the SNDR is improved by 5.65 dB at small input amplitudes. As a result, the Schreier figure of merit (FoM) for SNDR and DR is 183.2 and 190.4 dB, respectively.

This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma (ΔΣ) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH ΔΣ ADC were evaluated. The proposed ADC is fabricated and measured in a 180 nm CMOS process, achieving a DR, peak SNDR, and SFDR of 100.2 dB, 98.5 dB, and 116.7 dB, respectively, within a 2.56 kHz bandwidth, consuming only 20.1 μW. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR are 179.6 dB and 181.3 dB, respectively. The measurement results of the prototype 3-0 MASH ΔΣ ADC closely matched the theoretical predictions. This consistency between the measurements and the theoretical analysis confirms the reliability of the design approach in achieving the expected performance.

This paper presents an implantable pressure sensor readout system (IPRO) which can work at low voltage and does not need internal low dropout regulator (LDO). This paper has made a series of optimizations for power consumption. The power supply of IPRO uses 434 MHz energy harvesting (EH), which only uses two-stage rectification and is equipped with corresponding ultra-low power undervoltage locking (UVLO) circuit. The analog front-end (AFE) and signal processing parts use current mode and differential pseudo phase locked loop (DPPLL), which can work stably under low voltage and maintain a certain degree of accuracy and power rejection ability. The wireless data transmission part adopts the impulse ultra-wide band (IR-UWB) scheme. Its ultra-low power consumption allows it to be powered by a charge pump, which is the first time it has been proposed in implantable systems. In order to further optimize power consumption, a simplest encoding circuit suitable for the front-end output form was proposed, and a power oscillator (PO) with accelerated start-up was used to optimize area and power consumption. The system is implemented in 180 nm Complementary Metal Oxide Semiconductor (CMOS) process, with a chip area of 1.1 * 1.0 mm ² . The measurement results indicate that the typical working voltage of the IPRO is 0.8 V, the typical power consumption is 11.8 μW, and the accuracy is 1.11 mmHg. Compared with existing designs, there is a significant optimization in supply voltage and power consumption.

This article presents a dynamic range (DR) enhanced discrete-time delta–sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5-bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital-to-analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold ( $V_{\text {TH}}$ ) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7-dB DR and 92.4-dB signal-to-noise-and-distortion ratio (SNDR) at a 700-Hz bandwidth with only 2.3- $\mu \text{W}$ power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.

Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.