Lei Lu

This study systematically reveals an intrinsic ternary trade-off among field-effect mobility (μFE), photoresponse, and negative bias stress (NBS) stability in amorphous indium zinc oxide (IZO) thin-film transistors (TFTs). Precise control over oxygen vacancy (VO) concentration and amorphous microstructures is achieved through two independent modulation strategies involving N2 doping and sputtering target composition adjustment. Comprehensive electrical characterizations demonstrate that VO acts as a primary controlling factor within the structurally stable amorphous network, while the overall relationships is additionally bounded by defect-state redistribution and network disorder. While an optimal VO concentration significantly promotes μFE and photoresponse through enhanced carrier density and efficient photogeneration, NBS stability is simultaneously compromised by intensified defect-assisted charge trapping and carrier ionization. This trade-off persists regardless of whether the modulation induces monotonic or nonmonotonic behaviors. These findings provide critical physical insights and design guidelines for tailoring oxide TFTs to diverse application-specific requirements.

Monolithic 3D integration of oxide thin-film transistors provides an approach to continue Moore's Law. Crystalline indium oxide (In₂O₃) is particularly attractive owing to its high electron mobility and low contact resistance. However, its practical deployment is hindered by the difficulty of fabricating crystalline In₂O₃ under BEOL-compatible conditions and by the intrinsic instability of surface oxygen. In this work, we demonstrate an atomic-layer-deposition-enabled stabilization strategy that simultaneously achieves high mobility, strong electrostatic control, and exceptional stability in crystalline In₂O₃ transistors. The afforded devices exhibit a high electron mobility of 92.8 cm²/V·s, a positive threshold voltage of 0.67 V, a steep subthreshold swing of 64.5 mV/dec, and fairly small threshold voltage shifts of -5.6 and 18.6 mV under negative- and positive-bias stress, respectively. Furthermore, the devices show good resistance to forming gas annealing, with small threshold voltage shifts and no degradation in subthreshold swing or on-current. This work not only provides valuable insight into the origin of instability for crystalline oxide semiconductors, but also demonstrates a practical fabrication approach at CMOS BEOL-compatible temperatures to achieve both high performance and high stability for oxide transistors, thereby highlighting the high promise of indium oxide transistors for advanced M3D integration.

In this work, we demonstrate self-aligned top-gate (SATG) indium gallium oxide (IGO) field-effect transistors (FETs) fabricated by atomic layer deposition (ALD) for capacitor-less (2T0C) DRAM applications. The devices exhibit enhancement-mode (E-mode) operation with a high field-effect mobility of 77.5 cm²/V·s and excellent bias stability. Owing to the minimized parasitic capacitance in the SATG structure and post-deposition annealing (PDA) enabled E-mode IGO channel, the 2T0C cells exhibit a small coupling-induced voltage drop (ΔV_SN < 0.06 V) and a long retention over 10⁴ s at 0 V hold. These results demonstrate the strong potential of SATG IGO FETs for BEOL-compatible 2T0C DRAM applications.

Ultraviolet photodetectors (UV‐PDs) based on wide‐bandgap oxide semiconductors (OSs) hold broad prospects in scientific, civil, and especially fire alarm applications. However, the hotly pursued flexible and hetero‐integration capabilities are hindered by the high processing temperature of mainstream Ga ₂ O ₃ UV‐PDs, while the selective UV detection capability of low‐temperature OS (LT‐OS) is undermined by the pronounced contradictory effects of abundant native defects on electric and optoelectrical properties. Herein, a heterointerface‐functionalized Schottky photodiode (HF‐SPD) is proposed to realize high‐performance LT‐OS UV‐PD. Due to the sophistically modulated Schottky contact and defect distribution, ultralow dark current and remarkable photoresponse are simultaneously achieved in In ₂ O ₃ HF‐SPDs. Under the typical 360‐nm UV illumination, the responsivity ( R ) and detectivity ( D ^* ) respectively reach 27.75 A W ⁻¹ and 2.036 × 10 ¹³ Jones, enabling the early‐fire‐warning capability. Moreover, the HF‐SPD possesses unique wavelength selectivity and bias‐tunable photoelectrical characteristics. By feeding such multidimensional feature data into the multi‐layer perceptron (MLP) neural network, the pattern recognition of the spectrum delivers a remarkable accuracy of 99.94%, ensuring the precise identification of combustion materials. Such an intelligent fire warning system demonstrates the prospects of algorithm‐boosted LT‐OS HF‐SPDs in ubiquitous intelligent systems, such as wearable photodetection and in‐sensor computing (ISC) devices.

The degradation behavior of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under alternating current (ac) off-state stress (OSS) with a direct current (dc) voltage bias is systematically investigated for the first time. Degradation is governed by the interplay between peak voltage duration, which controls trap emission and hot-carrier (HC) generation, and base voltage duration, which enables trap refilling. The applied dc drain bias further modifies the electric field in the p-n junction, with negative bias enhancing the field and accelerating HC degradation, while positive bias weakens the field and promotes carrier recapture. Supported by experiments and TCAD simulations, a unified emission-recapture model is proposed, offering clear guidance for improving device reliability in circuit applications.

Organic light‐emitting diodes (OLEDs) are central to high‐end displays and solid‐state lighting due to their small thickness and high flexibility, wide color gamut, and low power consumption. While solution processing offers simplicity and cost advantages for polymer‐based OLEDs, vacuum thermal evaporation (VTE) remains the dominant method for the commercial production of high‐performance small‐molecule OLEDs, owing to its precise control over film thickness, material purity, and multilayer integration. However, to meet the demands of display applications for higher performance, lower cost and more diverse forms (such as flexibility and high resolution), it is crucial to continuously optimize the VTE process. Meanwhile, although solution processing remains the predominant approach for perovskite light‐emitting diodes (PeLEDs), recent exploratory efforts have investigated VTE as an alternative route, thereby opening opportunities to transfer process insights from OLEDs to PeLEDs. This review aims to systematically summarize the application foundation and optimization strategies of VTE technology in OLEDs, and to explore how these mature practices can inform the process development and device design of vacuum‐evaporated PeLEDs.

Negative bias illumination stress (NBIS) instability presents a significant challenge for the application of amorphous InGaZnO4 (a-IGZO) thin-film transistors (TFTs) in active-matrix displays. In this paper, we demonstrate the effectiveness of incorporating split metal lines to enhance the NBIS stability with elevated-metal metal-oxide (EMMO) a-IGZO TFTs. The negative shift in subthreshold current after NBIS is successfully reduced from 3.92 V to 0.54 V when the width of the metal line reaches 2.0 lm, which is now predominantly caused by negative gate bias induced redistribution of pre-existing ionized oxygen vacancies in the channel a-IGZO. The enhanced NBIS stability is achieved through the illumination shielding effect by the metal lines and passivation of oxygen vacancies under the metal lines by oxygen laterally diffused from the spacing regions between the metal lines. The less degraded a-IGZO regions under the metal lines determined the overall performance of the a-IGZO TFT after NBIS.

This work presents a voltage pulse modulation strategy to effectively mitigate self-heating degradation in polycrystalline silicon thin-film transistors. By applying synchronized voltage stress (SVS) with optimized pulse parameters, the proposed method significantly suppresses channel temperature buildup and reduces device degradation. A predictive thermal model, rigorously validated through coupled simulations and experimental measurements, enables precise control of temperature dynamics under diverse operating conditions. Experimental demonstrations using light-emitting diode-integrated driver circuits reveal substantially improved operational stability under SVS, in sharp contrast to the rapid performance degradation observed with continuous stress. This purely electrical approach requires no structural modifications and offers a practical and cost-effective solution to enhance the reliability of advanced display technologies.